Unformatted text preview: Designing at this level is similar to C programming. Project Description/Requirements 1) We want you to code your FSM in Behavioral Verilog. Be creative with your FSM but at least one state is required. 2) One test bench and at least one module for your FSM 3) Clear comments to your code including comments in your test bench that make it clear how you are testing your module(s). Report Layout 1) A cover page containing names (max of two), student numbers, and project title. 2) A paragraph on the general description of your FSM (Finite State Machine). 3) A block diagram of FSM module(s). Please label all inputs and outputs. 4) A block diagram of how the module(s) and test bench are connected. 5) A state diagram of your FSM with data flow. 6) A copy of your simulation waveform results with enough comments to make it clear that your design functions correctly. 7) A copy of your code....
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This note was uploaded on 08/23/2009 for the course EE 6235 taught by Professor Carlsechen during the Fall '06 term at University of Texas at Dallas, Richardson.
- Fall '06