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EE6325prj1 - Designing at this level is similar to C...

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DESCRIPTION FOR VERILOG/VHDL PROJECT #1 Due August 31 7pm (start of class) Late Penalty: 10% per weekday (M-F) Project Introduction This project will be relatively simple, but we would like you to get a clear idea of what you would like to build for your FSM. This design does not have to be used for your final project, but with a little planning now, you will not have to create a new design at the end of the quarter. If you make your design scalable, you will not have to redo your design if it synthesizes to a small design. Reviewing what Verilog code is synthesizable will make your life much easier when you get to Project 3. In this project, we want you to build a Finite State Machine (FSM) using Behavioral Verilog. Behavioral Verilog is the highest level of abstraction without details for hardware implementation. You will not have to define gates in your code; we will have a program later this quarter to translate your behavioral Verilog code into structural Verilog code.
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Unformatted text preview: Designing at this level is similar to C programming. Project Description/Requirements 1) We want you to code your FSM in Behavioral Verilog. Be creative with your FSM but at least one state is required. 2) One test bench and at least one module for your FSM 3) Clear comments to your code including comments in your test bench that make it clear how you are testing your module(s). Report Layout 1) A cover page containing names (max of two), student numbers, and project title. 2) A paragraph on the general description of your FSM (Finite State Machine). 3) A block diagram of FSM module(s). Please label all inputs and outputs. 4) A block diagram of how the module(s) and test bench are connected. 5) A state diagram of your FSM with data flow. 6) A copy of your simulation waveform results with enough comments to make it clear that your design functions correctly. 7) A copy of your code....
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