EE6325prj2

EE6325prj2 - 8) Each diffusion contact must be DOUBLED. 9)...

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PROJECT #2 INVERTER DESIGN AND LAYOUT Due: Tuesday, September 19 At the Beginning of Class Late Penalty: 10% per weekday (M-F) Project Introduction For this project you will be using the Cadence Design tools to design, layout and characterize an inverter. This project will get you familiar with Cadence and also with the simulation of the layouts that you create. Project Description/Requirements 1) Review the Cadence tutorial. 2) Layout, extract and simulate the inverter. 3) You will be designing a symmetrical inverter with equal t LH and t HL (measured from 50% to 50%). (Delay difference must be within 5ps.) 4) The input slew rate is 60ps (time for input to go from high to low and vice versa). 5) Assume a 25fF load capacitance when simulating. 7) The poly gates for the two transistors must be vertically aligned.
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Unformatted text preview: 8) Each diffusion contact must be DOUBLED. 9) DESIGN OBJECTIVE: Minimize the bounding box area of your inverter layout while minimizing the energy-delay product (EDP). Report Layout 1) A cover page containing: Student names (max 2) including student number Clearly state your energy (E), delay (D), EDP, and the area (widths & lengths are measured from Top RX layer to Bottom RX layer) on the front. 2) Inverter layout with rulers (from cadence) showing the dimensions of the inverter. 3) Waveforms showing t LH and t HL times measured with AWAVES. 4) Show EDP vs. Delay plot. 5) Netlist and HSPICE file Grading Breakdown 50% Functional correctness of the inverter; delay & other specifications met 25% Inverter EDP and area 25% Report clarity and completeness...
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