EE6325prj3

EE6325prj3 - EE 6325 Project #3 SYNOPSYS PROJECT Due: Sep...

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EE 6325 Project #3 SYNOPSYS PROJECT Due: Sep 28 At The Beginning of Class (10% late penalty per week day) Project Introduction For this project you will use Synopsys to generate a mapped netlist based on the library of cells which we have provided. After running Synopsys, you will have a better idea of the complexity of your design as well as an exact cell count. This project will also give you a good idea of what cells you will be creating for your own library. Project Description/Requirements 1) Setup Cadence and Synopsys accounts. 2) Work through the Synopsys tutorial. 3) From the tutorial you will open your verilog code and create a netlist based on the library that we have provided. 4) Print out the report showing the total number of cells used for your design. The report will be generated by Synopsys. 5) Take the mapped verilog that you created and concatenate it with the header.v file that we have provided. 6) Test the code with Verilogger and obtain graphical waves of the mapped
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EE6325prj3 - EE 6325 Project #3 SYNOPSYS PROJECT Due: Sep...

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