EE6325prj4 - credit. What To Turn In (points are deducted...

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EE 6325 VLSI Design Project #4: D Flip-Flop Due: Thursday Oct 19 At The Beginning of Class Project Introduction For this project you will be using the Cadence Design tools to layout and characterize a D-Flip-Flop. Project Goals 1) Minimize diffusion breaks and cell width 2) Then minimize cell height 1) Follow the DFF design as shown in class. 2) A minimum of two diffusion contacts per connection to diffusion are required. 3) Input/output pins must lie on a grid (an integer multiple of the grid spacing) 4) Minimize the use of vertical metal2, and no horizontal metal2. 5) The input slew rate is 60ps (time for input to go from high to low and vice versa). 6) Assume a 20fF load capacitance when simulating 7) Implement an asynchronous reset for the DFF. 8) The DFF cell has 3 input pins (D, Clk, reset (active high or low) and one output pin). 9) Output can be Q or Q , but remember the design with the minimum size gets full
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Unformatted text preview: credit. What To Turn In (points are deducted for anything missing) 1) A cover page containing all the following information. Name, student number, and project title D Flip-Flop times: Tsetup, Tsetup (optimal), Thold, T clk->Q , and T D->Q o All times are worst case of course! Clearly state your width and height on the front. 2) Please include a short report describing the following how you found your D Fip-Flop times how you came up with your layout 3) D Flip-Flop layout with rulers showing the dimensions of the cell. Show the uniform distance between your pins Show height & width of entire cell 4) Waveforms showing how you computed Tsetup, Tsetup (optimal), Thold, T clk->Q , and T D->Q . 5) Netlist with parasitics and HSPICE (.sp) file Grading Breakdown 1) Correct functionality 50% 2) Cell width and height 20% 3) Report 30%...
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This note was uploaded on 08/23/2009 for the course EE 6235 taught by Professor Carlsechen during the Fall '06 term at University of Texas at Dallas, Richardson.

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