EE6325prj5

EE6325prj5 - EE 6325 VLSI Design PROJECT #5: Cell Library...

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EE 6325 VLSI Design PROJECT #5: Cell Library Due: Nov. 2 At The Beginning of Class Project Introduction For this project you will be creating your standard library of cells which will be used for your final project. In this project, you will need to generate abstract views of your cells. This is covered in the Cadence tutorial. Project Goals 1) Layout and verify the following cells: Inverter Nand2, Nand3, Nand4 Nor2, Nor3 XOR2, XNOR2 AOI_12, AOI_22 OAI_12, OAI_22 D-Flip Flop 2) All of your cells should be created such that when placed side by side next to each other, no DRC errors occur. All pins must be aligned horizontally as well, with uniform spacing. 1) 2) All diffusion contacts must be at least doubled. 3) The input slew rate is 60ps. 4)
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EE6325prj5 - EE 6325 VLSI Design PROJECT #5: Cell Library...

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