EE6325prj6 - PROJECT#6 Final Project Layout Verification...

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Due: Tuesday Nov. 21 (7p) Project Introduction For this project you will take your Verilog/VHDL code from projects 1 & 3 and lay it out using the cells that you generated in your cell library. Project Goals 1) Automatic placement and routing of your design using Cadence’s Encounter 2) Run DRC (design rule checker) and LVS (layout versus schematic) 3) Test the final layout 4) Run Pathmill on the extracted layout to get list of worst signal paths 1) Use an output capacitance of 20fF for all your outputs when testing 2) At least 100 cells. What To Turn In (points are deducted for anything missing) 1) A cover page containing all the following information. Name, student number, “EE6325 ”, and project title 2) Formal Report
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This note was uploaded on 08/23/2009 for the course EE 6235 taught by Professor Carlsechen during the Fall '06 term at University of Texas at Dallas, Richardson.

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