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lecture31

# lecture31 - Lecture#31 ANNOUNCEMENTS Prof Kings office...

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Lecture 31, Slide 1 EECS40, Fall 2003 Prof. King Lecture #31 ANNOUNCEMENTS Prof. King’s office hours this week are cancelled OUTLINE » Fan-out » Propagation delay » CMOS power consumption » Timing diagrams Reading (Rabaey et al .) Chapter 1.3, pp. 21-22 & 24-28 Chapter 5.2 & 5.5, pp. 148-149 & 173-184 Chapter 6.2.1, pp. 204-207, 215-216 Lecture 31, Slide 2 EECS40, Fall 2003 Prof. King Fan-Out Typically, the output of a logic gate is connected to the input(s) of one or more logic gates • The fan-out is the number of gates that are connected to the output of the driving gate: fan-out =N driving gate 1 2 N • Fanout leads to increased capacitive load on the driving gate, and therefore longer propagation delay – The input capacitances of the driven gates sum, and must be charged through the equivalent resistance of the driver

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Lecture 31, Slide 3 EECS40, Fall 2003 Prof. King Effect of Capacitive Loading When an input signal of a logic gate is changed, there is a propagation delay before the output of the logic gate changes. This is due to capacitive loading at the output. C L + v OUT + v IN v IN v OUT The propagation delay is measured between the 50% transition points of the input and output signals. (Ref. Lecture 16, Slides 3&4) Lecture 31, Slide 4 EECS40, Fall 2003 Prof. King Model the MOSFET in the ON state as a resistive switch: Case 1 : V out changing from High to Low (input signal changed from Low to High) NMOSFET(s) connect V out to GND t pHL = 0.69 × R n C L Calculating the Propagation Delay V DD Pull-down network is modeled as a resistor Pull-up network is modeled as an open switch C L + v OUT v IN = V DD R n
Lecture 31, Slide 5 EECS40, Fall 2003 Prof. King Calculating the Propagation Delay (cont’d) Case 2 : V out

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