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Unformatted text preview: Lecture 36, Slide 1 EECS40, Fall 2003 Prof. King Lecture #36 ANNOUNCEMENT Students in the Thursday 5-8PM lab session should contact the TA, to arrange to take Quiz #2 OUTLINE CMOS process flow Circuit extraction from layout Lecture 36, Slide 2 EECS40, Fall 2003 Prof. King Challenge: Build both NMOS & PMOS transistors on a single silicon chip NMOSFETs need a p-type substrate PMOSFETs need an n-type substrate Requires extra process steps! CMOS Technology oxide p-well n-type Si n+ n+ p+ p+ Lecture 36, Slide 3 EECS40, Fall 2003 Prof. King oxide n-type wafer *Create p-well Grow thick oxide *Remove thick oxide in transistor areas (active region) Grow gate oxide Deposit & *pattern poly-Si gate electrodes *Dope n channel source and drains (need to protect PMOS areas) Deposit insulating layer (oxide) *Open contact holes Deposit and *pattern metal interconnects *Dope p-channel source and drains (need to protect NMOS areas) At least 3 more masks, as compared to NMOS process...
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This note was uploaded on 08/23/2009 for the course EECS 40 taught by Professor Chang-hasnain during the Fall '08 term at University of California, Berkeley.
- Fall '08