lecture39 - Lecture #39 ANNOUNCEMENTS Pick up graded HW...

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Lecture 39, Slide 1 EECS40, Fall 2003 Prof. King Lecture #39 ANNOUNCEMENTS Pick up graded HW assignments and exams (278 Cory) Lecture #40 will be the last formal lecture. Class on Friday will be dedicated to a course review (with sample problems). Discussion sections this week will cover sample problems (review for the final exam) Deadline for “Best Tutebot” contest: 12/4 at 8 PM. Prof. King will hold extra office hours this Thursday afternoon OUTLINE » Transistor scaling » Silicon-on-Insulator technology » Interconnect scaling Reading (Rabaey et al .): Sections 2.5.1, 3.5, 5.6 Lecture 39, Slide 2 EECS40, Fall 2003 Prof. King Transistor Scaling • Steady advances in manufacturing technology (particularly lithography) have allowed for a steady reduction in transistor size. ~13% reduction/year (0.5 × every 5 years) • How should transistor dimensions and supply voltage ( V DD ) scale together? Average minimum L of MOSFETs vs. time
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Lecture 39, Slide 3 EECS40, Fall 2003 Prof. King Scenario #1: Constant-Field Scaling • Voltages and MOSFET dimensions are scaled by the same factor S >1, so that the electric field remains unchanged t ox / S V DD / S V DD L / S x j / S x j N A × S Doping N A S 1.4 Lecture 39, Slide 4 EECS40, Fall 2003 Prof. King (a) MOSFET gate capacitance: S C S t S W S L C W L C gate ox ox ox gate = = = ε Impact of Constant-Field Scaling (b) MOSFET drive current:
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lecture39 - Lecture #39 ANNOUNCEMENTS Pick up graded HW...

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