lecture40 - ANNOUNCEMENTS Final Exam When Wednesday 12/10...

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ANNOUNCEMENTS Final Exam: When : Wednesday 12/10 12:30-3:30PM Where : 10 Evans (last names beginning A-R) 60 Evans (last names beginning S-Z) Comprehensive coverage of course material Closed book; 3 sheets of notes & calculator allowed For Chunlong’s students (Lab Sections 17 & 20): Section 17 (Wed 3-6 PM) students should attend an alternate section, to have their Tutebots checked off before Thu. 8 PM Students in Lab Sections 17 & 20 (Wed 3-6 PM & Thu 5-8 PM) can receive their deposit checks back next week. Prof. King’s Office Hours tomorrow: 1-5 PM, 476 Cory Final Exam Topics 1. Circuit analysis 2. Equivalent circuits 3. Op-amp circuits 4. First-order circuits / transient response 5. Semiconductor properties, pn diodes 6. MOSFET devices and circuits 7. Logic circuits (including delay analysis) 8. CMOS process & layout Microelectronics Technology in the 21 st Century Outline • Introduction • Scaling Si Transistors to the Limit • Beyond Scaling • Conclusion Reference Reading Rabaey et al .: Section 2.5.2 The growth of the semiconductor industry has been tied to transistor scaling IC Technology Advancement Technology Scaling Investment Better Performance/Cost Market Growth 2000 2005 2010 2015 2020 1 10 100 GATE LENGTH (nm) YEAR LOW POWER HIGH PERFORMANCE ITRS 2001 Projection $141B in 2002 Intel’s 90 nm CMOS Technology Used for volume manufacturing of ICs on 300 mm wafers beginning 4Q03 L g = 50 nm T ox = 1.2 nm • Strained Si channel 14 nm CMOS Transistors Hokazono et al. , Toshiba Corporation, presented at the International Electron Devices Meeting (San Francisco, CA) Dec. ‘02 • 1.3 nm SiO x N y gate dielectric •Po ly-S i 0.9 Ge 0.1 gate
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Substrate Gate Source Drain M etal-O xide-S emiconductor F ield-E ffect T ransistor: Bulk-Si MOSFET Scaling Leakage current is the main challenge to scaling To suppress leakage, we need to employ: Higher body doping Æ lower carrier mobility, higher junction capacitance, increased junction leakage Thinner gate dielectric Æ higher gate leakage Ultra-shallow S/D junctions Æ higher R series L eff N sub X j L g T ox Desired characteristics : High ON current ( I dsat ) Low OFF current Outline Introduction Scaling Si Transistors to the Limit Beyond Scaling Conclusion Gate Advanced MOSFET Structures Must control leakage in order to scale down L g Most of the leakage occurs far from the SiO 2 interface Let’s get rid of it!
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lecture40 - ANNOUNCEMENTS Final Exam When Wednesday 12/10...

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