Lecture 08 - Scan 01

# Lecture 08 - Scan 01 - Testing and Testable Design...

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1 1 Testing and Testable Design Testing and Testable Design `x{Üwtw aÉâÜtÇ| Dept. of EE Univ. of Texas at Dallas 2 Scan and Boundary Scan Session 08 Session 08

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2 3 Basic Concept 4 Architectural View A sequential circuit is viewed as A combinational logic block, with Primary inputs x 1 , x 2 , …, x n Primary outputs z , z , …, z m State inputs (present state) y , y , …, y k State outputs (next state) Y , Y , …, Y i and are respectively the input and output of FF x 1 x 2 x n y 1 y 2 y k z 1 z 2 z m Y 1 Y 2 Y k FF k FF 2 FF 1 Combinational logic block FF FF FF
3 5 Test Generation in Scan Hence, for purposes of test development State inputs treated as primary inputs State outputs treated as primary outputs By reducing test generation for sequential circuits to test generation for combinational circuits, scan Reduces test development cost In many cases, enables attainment of acceptable fault coverage x 1 x 2 x n y 1 y 2 y k z 1 z 2 z m Y 1 Y 2 Y k Combinational logic block 6 Scan as a DFT Method In scan DFT (design for testability) methodology, flip-flops (or latches) designed to support two modes Normal mode : Flip-flops configured as in the original circuit Test mode : Flip-flops configured as one or more shift- registers, called scan registers or scan chains Most Common SSF cell D Q FF mc D S Mux (or TC refers to Mode Control) Clock

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4 7 Scan Structure Testing using scan In normal mode, responses at state outputs captured in flip-flops Circuit then configured in the test mode Scan registers clocked The output of the last flip-flop in scan chain observed At the same time, values to be applied at state inputs in the subsequent test shifted into flip-flops SFF SFF SFF Combinational logic PI PO SCANOUT SCANIN TC: Test Mode TCK (or MCK/SCK): Clock TC, TCK 8 Applying Test in Scan Shift Register Test: TC=1 (scan mode) and apply the 001100… Test length: n sff +4 Scan Test: TC=1 (scan mode) Shift yi values in FFs. Put xi values in PIs. TC=0 (normal mode) and check zi’s. Apply clock to TCK (still normal mode). TC=0 (scan mode) and shift Yi’s out for check. x2 x1 z1 z2 y2 y1 Y2 Y1 Combinational logic PI Present state PO Next state SCANIN TC SCANOUT
5 9 Applying Test in Scan (cont.) Total scan test length (number of clocks) ( n sff +4)+ ( sff +1) n comb + (n sff -1) = ( comb +2) sff + comb +3 comb = number of combinational vectors sff = number of scan flip-flops Without considering shift register test: ( sff +1) n comb + (n sff -1) x2 x1 z1 z2 PI PO SCANIN SCANOUT y1 y2 Y1 Y2 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 TC Don’t care or random bits 10 Applying Test in Scan (cont.) Scan register must be tested prior to application of scan test sequences.

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## This note was uploaded on 08/23/2009 for the course EE 6303 taught by Professor Mehrdadnourani during the Fall '08 term at University of Texas at Dallas, Richardson.

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Lecture 08 - Scan 01 - Testing and Testable Design...

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