Lecture 08 - Scan 02

Lecture 08 - Scan 02 - Testing and Testable Design...

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1 1 Testing and Testable Design Testing and Testable Design `x{Üwtw aÉâÜtÇ| Dept. of EE Univ. of Texas at Dallas 2 Scan Design for Testability Session 08 Session 08
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2 3 Boundary Scan 4 Board-Level Testing Each chip used in a PCB is pretested by the chip’s vendor and declared fault-free Testing at board level focuses on Inter-chip interconnect faults Opens + Caused when chip pins do not bond properly to board + That occur in PCB traces due to defects during PCB manufacturing Shorts caused when extra solder flows between pins or PCB traces
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3 5 Board-Level Testing (cont.) Testing at board level focuses on Faults internal to chips Faults induced due to improper handling, e.g., excessive heat or shock during PCB assembly Faulty behaviors that become apparent only when a chip is integrated into a PCB, e.g., the ability to drive a large load These defects + More likely to occur in pad drivers and pad receivers + However, may also occur in system logic , i.e., on-chip logic circuit Since repair possible, diagnosis also important Board-level DFT supports Testing and diagnosis of faults in inter-chip interconnects (including pad drivers and receivers) In-situ re-testing of system logic Debugging of system design 6 Board-Level Testing (cont.) Possible approaches for board testing Consider the entire board as one circuit and generate tests: Not possible because The circuit too large for ATPG tools Net-list of most chips unavailable In-circuit testing Probes were used to access input/output pins of chips Care had to be taken to ensure probes driving values did not damage output pins No longer used because + Pins are too small and too close to be reliably probed + Pins at bottoms of chips cannot be probed in multi-layered PCBs Boundary scan
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4 7 Boundary Scan Boundary scan used to test Chips-on-board (COB) systems, where chips are mounted on a printed circuit board (PCB) Multi-chip modules (MCM), where bare-die are integrated on a silicon or a PCB-like substrate A COB system is obtained by Using a PCB that contains traces, i.e., metal connectors that constitute inter-chip interconnects Bonding (e.g., soldering) chips on the PCB 8 Boundary Scan Structure Boundary scan incorporates DFT circuitry that allows direct access to chip input and output pins via scan chains A board contains chips from multiple manufacturers Boundary scan circuits must interoperate to achieve above objectives Hence, a standard, namely IEEE Std 1149.1, defined
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5 9 Example: A Board Without Boundary Scan 1 2 31 2 3 4 Chip 1 Chip 2 x 1 x 2 x 1 z 5 z 4 z 1 z 1 z 4 z 3 z 2 Board An I/O pin A power/ground pin Edge connector On-chip system logic b 1 b 2 Consider an example board. Especially note Bi-directional driver/receiver – Pin 3 of Chip 1 Tri-state driver – Pin 2 of Chip 2 10 Example: Testing Without Boundary Scan (cont.) Assume that
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Lecture 08 - Scan 02 - Testing and Testable Design...

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