e_BIST - 10/06/11 Based on text by S. Mourad...

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Unformatted text preview: 10/06/11 Based on text by S. Mourad "Priciples of Electronic Systems" Digital Testing: Built-in Self-test Outline BIST and embedded testing Why BIST Primitive polynomials LFSR Response compression BILBO Define Built-In Self-Test Implement the function of automatic test equipment (ATE) on circuit under test (CUT). Hardware added to CUT: Pattern generation (PG) Response analysis (RA) Test controller CUT Stored Test Patterns Stored responses Pin Electronics Comparator hardware Test control HW/SW ATE PG RA CUT Go/No-go signature Test control logic CK BIST Enable Built-in self-test Disadvantage of LSSD & other scan techniques: 1. Test generation necessary for combinational part 2. Long test time since test have to be shifted in & out 3. Only stuck-at faults are tested - not good for VLSI Built-in self test Test generation is NP complete. This prompted a search for built-in structures * Built-in self test BIST is an alternative to automatic test vector generation * Test generation & verification done by circuits built into the chip * Pseudo-random test vector generation is accomplished by using shift registers Built-in self-test in VLSI Test patterns generated on chip responses to test evaluated on chip external operations only to initialize test & clock go no go results additional pins & silicon area minimized Built-in self test types operation (concurrent or not) test design (exhaustive or not) test vector generation (deterministic or pseudorandom) data compression (full or compresses test vectors) A general built-in self test approach Built-in self test * Deterministic testing identifies test vectors to detect specific faults * Pseudorandom testing detects # of faults by any test vector * Fault coverage increases rapidly at the beginning and slows down towards the end * The response data is compressed using a signature analysis * Linear feedback shift registers (LFSR) used to generate test vectors and compress responses Pseudorandom Integers 5 1 3 7 6 2 4 Start +3 Sequence: 2, 5, 0, 3, 6, 1, 4, 7, 2 . . . 5 1 3 7 6 2 4 Start +2 Sequence: 2, 4, 6, 0, 2 . . . X k = X k-1 + 3 ( modulo 8) X k = X k-1 + 2 ( modulo 8) Maximum length sequence: 3 and 8 are relative primes . Pseudo-Random Pattern Generation Standard Linear Feedback Shift Register (LFSR) Produces patterns algorithmically repeatable Has most of desirable random # properties May not cover all 2 n input combinations Long sequences needed for good fault coverage either h i = 0, i.e., XOR is deleted or h i = X i Initial state (seed): X , X 1 , . . . , X n- 1 must not be 0, 0, . . . , 0 Pseudo-Random Pattern Generator Y 1 Y 2 Y 3 Q Q D Q Q D Q Q D Y 1 Y 2 Y 3 Clk Y Q Q D Q Q D Q Q D Clk Y (c) (b) Q Q D Q Q D Q Q D Y 1 Y 2 Y 3 Clk Y0 (a) Various LFSR configurations Pseudo-random Patterns (a) (b) (c) Clk Y0 Y1Y2Y3 ClkY0 Y1Y2Y3 ClkY0 Y1Y2Y3 1 001 1 001 1 001 1 1 100 1 100 1 1 100 2 1 110 2 010 2...
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This note was uploaded on 08/23/2009 for the course EE 6303 taught by Professor Mehrdadnourani during the Fall '08 term at University of Texas at Dallas, Richardson.

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e_BIST - 10/06/11 Based on text by S. Mourad...

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