02_ARM_Processor_Core_and_Instruction_Sets

r1table1 r2table2 r0r1 r0r2 r1r14 r2r24 table1

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Unformatted text preview: ffset to the program counter, r15 – ARM assembler has a “pseudo” instruction, ADR • As an example, a program which must copy data from TABLE1 to TABLE2, both of which are near to the code COPY ADR r1,TABLE1 ;r1 points to TABLE1 ADR r2,TABLE2 ;r2 points to TABLE2 … TABLE1 … ;<source> … ;<destination> TABLE2 71/213 Single Register Load and Store Institute of Electronics, National Chiao Tung University • A base register, an offset which may be another register or an immediate value Copy Loop ADR ADR LDR STR ADD ADD ??? … r1,TABLE1 r2,TABLE2 r0,[r1] r0,[r2] r1,r1,#4 r2,r2,#4 TABLE1 … TABLE2 … 72/213 Base-plus-offset Addressing (1/3) Institute of Electronics, National Chiao Tung University • Pre-indexing LDR r0,[r1,#4] ;r0:=mem32[r1+4] – offset up to 4K, added or subtracted, (#-4) • Post-indexing LDR r0,[r1],#4 ;r0:=mem32[r1], r1:=r1+4 – equivalent to a simple register-indirect load, but faster, less code space • Auto-indexing LDR r0,[r1,#4]! ;r0:=mem32[r1+4], r1:=r1+4 – no extra time, auto-indexing performed while the data is being fetched from memory 73/213 Base-plus-offset Addressing (2/3) Institute of Electronics, National Chiao Tung University *Pre-indexed: STR r0, [r1, #12] Offset 12 Base Register r1 0x200 0x20c 0x5 r0 0x5 0x5 r0 0x5 Source Register for STR 0x200 Auto-update from: STR r0, [r1, #12] ! *Post-indexed: STR r0, [r1], #12 Updated Base Register Original Base Register r1 0x20c r1 0x200 Offset 12 0x20c 0x200 Source Register for STR 74/213 Base-plus-offset Addressing (3/3) • Copy Institute of Electronics, National Chiao Tung University Loop ADR ADR LDR STR ??? … r1,TABLE1 r2,TABLE2 r0,[r1],#4 r0,[r2],#4 TABLE1 … TABLE2 … • A single unsigned byte load LDRB r0,[r1] ;r0:=mem8[r1] – also support signed bytes, 16-bit half-word 75/213 Loading Constants (1/2) Institute of Electronics, National Chiao Tung University • No single ARM instruction can load a 32-bit immediate constant directly into a register – all ARM instructions are 32-bit long – ARM instructions do not use the instruction stream as data • The data processing instruction format has 12 bits available for operand 2 – if used directly, this would only give a range of 4096 • Instead it is used to store 8-bit constants, give a range of 0~255 • These 8 bits can then be rotated right through an even number of positions (i.e. RORs by 0,2,4,…,30) • This gives a much larger range of constants that can be directly loaded, though some constants will still need to be loaded from memory 76/213 Loading Constants (2/2) • This gives us: Institute of Electronics, National Chiao Tung University – – – – • 0~255 256,260,264,…,1020 1024,1240,…,4080 4096,4160,…,16320 To load a constant, simply move the required value into a register - the assembler will convert to the rotate form for us – MOV r0,#4096 • ;MOV r0,#0x1000 (0x40 ror 26) The bitwise complements can also be formed using MVN: – MOV r0,#0xFFFFFFFF • [0-0xff] [0x100-0x3fc,step4,0x40-0xff ror 30] [0x400-0xff0,step16,0x40-0xff ror 28] [0x1000-0x3fc0,step64,0x40-0xff ror 26] ;MVN r0,#0 Values that cannot be generated in this way will cause an error 77/213 Loading 32-bit Constant...
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This note was uploaded on 08/23/2009 for the course IEE 5016 taught by Professor Tian-sheuanchang during the Spring '05 term at National Chiao Tung University.

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