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02_ARM_Processor_Core_and_Instruction_Sets

02_ARM_Processor_Core_and_Instruction_Sets - Chapter 2 ARM...

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Chapter 2 ARM Processor Core and Instruction Sets Prof. Tian-Sheuan Chang
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1/213 Institute of Electronics, National Chiao Tung University Outline Processor programming model 32-bit instruction set 16-bit instruction set ARM processor core Software development
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2/213 Institute of Electronics, National Chiao Tung University Processor Programming Model
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3/213 Institute of Electronics, National Chiao Tung University ARM Ltd ARM was originally developed at Acron Computer Limited of Cambridge, England between 1983 and 1985 1980, RISC concept at Stanford and Berkeley universities first RISC processor for commercial use 1990 Nov, ARM Ltd was founded ARM cores licensed to partners who fabricate and sell to customers Technologies assist to design in the ARM application Software tools, boards, debug hardware, application software, bus architectures, peripherals etc…
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4/213 Institute of Electronics, National Chiao Tung University ARM Architecture vs. Berkeley RISC Features used load/store architecture fixed-length 32-bit instructions 3-address instruction formats Features unused register windows costly use shadow registers in ARM delayed branch not well to superscalar badly with branch prediction single-cycle execution of all instructions most single-cycle memory access multiple cycles when no separate data and instruction memory support auto-indexing addressing modes
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5/213 Institute of Electronics, National Chiao Tung University Data Size and Instruction set ARM processor is a 32-bit architecture Most ARM’s implement two instruction sets – 32-bit ARM instruction set – 16-bit Thumb instruction set
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6/213 Institute of Electronics, National Chiao Tung University Data Types ARM processor supports 6 data types 8-bits signed and unsigned bytes 16-bits signed and unsigned half-words, aligned on 2-byte boundaries 32-bits signed and unsigned words, aligned on 4-byte boundaries ARM instructions are all 32-bit words, word-aligned Thumb instructions are half-words, aligned on 2-byte boundaries Internally all ARM operations are on 32-bit operands; the shorter data types are only supported by data transfer instructions. When a byte is loaded form memory, it is zero- or sign-extended to 32 bits ARM coprocessor supports floating-point values
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7/213 Institute of Electronics, National Chiao Tung University Programming Model Each instruction can be viewed as performing a defined transformation of the states visible registers invisible registers system memory user memory
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8/213 Institute of Electronics, National Chiao Tung University Processor Modes ARM has seven basic operating modes Mode changes by software control or external interrupts user Running privileged operating system System 11111 _und Handling undefined instruction traps Undef 11011 _abt Processing memory faults Abort 10111 _svc Processing software interrupts (SWIs) SVC 10011 _irp Processing standard interrupts IRQ 10010 _fiq Processing fast interrupts FIQ 10001 User Normal user code User 10000 Registers Use Mode CPRS[4:0]
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