02_ARM_Processor_Core_and_Instruction_Sets

1 rm cond 00110 op 0 rn crd rot 8 bit immediate unused

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Unformatted text preview: by the coprocessor • Examples LDC P6,c0,[r1] STCEQL P5,c1,[r0],#4 111/213 Coprocessor Register Transfers • Move to ARM register from coprocessor Institute of Electronics, National Chiao Tung University MRC{<cond>} <CP#>,<Cop1>,Rd,CRn,CRm,{,<Cop2>} • Move to coprocessor from ARM register MCR{<cond>} <CP#>,<Cop1>,Rd,CRn,CRm,{,<Cop2>} 31 28 27 cond 1110 24 23 212019 Cop1 L CRn 16 15 12 11 CRd 87 54 3 0 CP# Cop2 1 CRm Load from coprocessor/store to coprocessor • Examples MCR P14,3,r0,c1,c2 MRCCS P2,4,r3,c3,c4,6 112/213 Breakpoint Instructions (BKPT-v5T only) Institute of Electronics, National Chiao Tung University • BKPT <16-bit immediate> • Used for software debugging purposes; they cause the processor to break from normal instruction execution and enter appropriate debugging procedures • BKPT is unconditional • Handled by an exception handler installed on the prefetch abort vector 113/213 Unused Instruction Space • Unused Arithmetic Instructions Institute of Electronics, National Chiao Tung University 28 27 22 212019 cond 000001 op 31 • Rn Unused Control Instructions 31 2322 212019 28 27 16 15 12 11 Rd 16 15 RS 12 11 8 7 65 4 3 1001 Rm 8 7 65 4 3 cond 00010 op 0 Rn CRd RS op 0 Rn CRd RS 0 op2 1 Rm cond 00110 op 0 Rn CRd #rot 8-bit immediate Unused Load/Store Instructions 31 28 27 25 23 21 24 22 2019 cond 000 P U B WL • 16 15 Rn 12 11 Rd RS 8 7 65 4 3 0 1 op 1 Rm Unused Coprocessor Instructions 31 28 27 23 21 24 22 2019 cond 1100 • 0 op2 0 Rm cond 00010 • 0 op 0 x Rn 16 15 12 11 CRd CP# 87 0 offset Undefined Instruction Space 31 28 27 2524 cond 011 xxxxxxxxxxxxxxxxxxxx 54 3 0 1 xxxx 114/213 Institute of Electronics, National Chiao Tung University 16-bit Instruction Set 115/213 Thumb Instruction Set (1/3) Mnemonic Instruction Institute of Electronics, National Chiao Tung University ADC ADD AND ASR B Bxx BIC BL BX CMN CMP EOR LDMIA LDR Add with carry Add AND Arithmetic Shift Right Branch Conditional Branch Bit Clear Branch with Link Branch and Exchange Compare Negative Compare EOR Load Multiple Load Word Lo Hi Condition Register Register Code ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ 116/213 Thumb Instruction Set (2/3) Mnemonic Instruction Institute of Electronics, National Chiao Tung University LDRB LDRH LSL LDSB LDSH LSR MOV MUL MVN NEG ORR POP PUSH ROR Load Byte Load Halfword Logical Shift Left Load Signed Byte Load Signed Halfword Logical Shift Right Move Register Multiply Move Negative Register Negate OR Pop Registers Push Registers Rotate Right Lo Hi Condition Register Register Code ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ 117/213 Thumb Instruction Set (3/3) Mnemonic Instruction Institute of Electronics, National Chiao Tung University SBC STMIA STR STRB STRH SWI SUB TST Subtract with Carry Store Multiple Store Word Store Byte Store Halfword Software Interrupt Subtract Test Bits Lo Hi Condition Register Register Code ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ 118/213 Thumb Instruction Format Institute of Electronics, National Chiao Tung University 119/213 Thumb-ARM Difference Institute of Electronics, National Chiao Tung University • Thumb instruction set is a subset of the ARM instruction set and the instructions operate on a restricted view of the ARM registers • Most Thumb instructions are executed unconditionally (All ARM instructions are execut...
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This note was uploaded on 08/23/2009 for the course IEE 5016 taught by Professor Tian-sheuanchang during the Spring '05 term at National Chiao Tung University.

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