02_ARM_Processor_Core_and_Instruction_Sets

12 32 bit product least significant institute of

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Unformatted text preview: D r5,r1,r3 ADD Rs,PC,#offset • Decrement r2 and check for zero ;PC is ADD address+8 SUBS r2,r2#1 BEQ LABEL … • ;dec r2 and set cc Multiply r0 by 5 ADD r0,r0,r0,LSL #2 • A subroutine to multiply r0 by 10 TIMES10 • MOV BL …… MOV ADD MOV r0,#3 TIMES10 r0,r0,LSL #1 r0,r0,r0,LSL #2 PC,r14 ;*2 ;*5 ;return Add a 64-bit integer in r1, r0 to one in r3, r2 ADDs r2,r2,r0 ADC r3,r3,r1 63/213 Multiply Instructions (1/2) • 32-bit Product (Least Significant) Institute of Electronics, National Chiao Tung University MUL{<cond>}{S} Rd,Rm,Rs MLA{<cond>}{S} Rd,Rm,Rs,Rn • 64-bit Product <mul>{<cond>}{S} RdHi,RdLo,Rm,Rs <mul> is (UMULL,UMLAC,SMULL,SMLAL) 64/213 Multiply Instructions (2/2) Institute of Electronics, National Chiao Tung University • Accumulation is denoted by “+=“ • Example: form a scalar product of two vectors Loop MOV r11,#20 MOV r10,#0 LDR r0,[r8],#4 LDR r1,[r9],#4 MLA r10,r0,r1,r10 SUBS r11,r11,#1 BNE Loop ;initialize loop counter ;initialize total ;get first component ;get second component 65/213 Count Leading Zeros (CLZ-V5T only) Institute of Electronics, National Chiao Tung University • CLZ{<cond>} Rd,Rm – set Rd to the number of the bit position of the most significant 1 in Rm; If Rm is zero, Rd=32 – useful for renormalizing numbers • Example MOV r0,#&100 CLZ r1,r0 ;r1:=23 • Example CLZ r1,r2 MOVS r2,r2,LSL r1 66/213 Data Transfer Instructions Institute of Electronics, National Chiao Tung University • Three basic forms to move data between ARM registers and memory – single register load and store instruction • a byte, a 16-bit half word, a 32-bit word – multiple register load and store instruction • to save or restore workspace registers for procedure entry and exit • to copy blocks of data – single register swap instruction • a value in a register to be exchanged with a value in memory • to implement semaphores to ensure mutual exclusion on accesses 67/213 Single Register Data Transfer Institute of Electronics, National Chiao Tung University • Word transfer LDR / STR • Byte transfer LDRB / STRB • Halfword transfer LDRH / STRH • Load singed byte or halfword-load value and sign extended to 32 bits LDRSB / LDRSH • All of these can be conditionally executed by inserting the appropriate condition code after STR/LDR LDREQB 68/213 Addressing Institute of Electronics, National Chiao Tung University • Register-indirect addressing • Base-plus-offset addressing – base register r0-r15 – offset, add or subtract an unsigned number immediate register (not PC) scaled register (only available for word and unsigned byte instructions) • Stack addressing • Block-copy addressing 69/213 Register-indirect Addressing Institute of Electronics, National Chiao Tung University • Use a value in one register (base register) as a memory address LDR r0,[r1] ;r0:=mem32[r1] STR r0,[r1] ;mem32[r1]:=r0 • Other forms – adding immediate or register offsets to the base address 70/213 Initializing an Address Pointer Institute of Electronics, National Chiao Tung University • A small o...
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This note was uploaded on 08/23/2009 for the course IEE 5016 taught by Professor Tian-sheuanchang during the Spring '05 term at National Chiao Tung University.

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