02_ARM_Processor_Core_and_Instruction_Sets

203213 debugger 12 institute of electronics national

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Unformatted text preview: uction selects various data registers – device ID register, bypass register, boundary scan register • Some public instructions – BYPASS: connect TDI to TDO with 1-clock delay – EXTEST: test the board-level connectivity, boundary scan register is connected • capture DR: captured by the boundary scan register • shift DR: shift out via TDO • update DR: new data applied to the boundary scan register via TDI – TNTEST: test the core logic – INCODE: ID register is connect 200/213 Macrocell Testing • Institute of Electronics, National Chiao Tung University • System chip is composed of the pre-designed macrocells with applicationspecific custom logic Various approaches to test the macrocells – test mode provided which multiplexes the signals in turn onto the chip – on-chip bus may support direct test access to macrocell pins – each macrocell may have a boundary scan path using JTAG extensions 201/213 ARM Debug Architecture (1/2) Institute of Electronics, National Chiao Tung University • Two basic approaches to debug – from the outside, use a logic analyzer – from the inside, tools supporting single stepping, breakpoint setting • Breakpoint: replacing an instruction with a call to the debugger Watchpoint: a memory address which halts execution if it is accessed as a data transfer address Debug Request: through ICEBreaker programming or by DBGRQ pin asynchronously 202/213 ARM Debug Architecture (2/2) Institute of Electronics, National Chiao Tung University • In debug state, the core’s internal state and the system’s external state may be examined. Once examination is complete, the core and system state may be restored and program execution is resumed. • The internal state is examined via a JTAG-style serial interface, which allows instructions to be serially inserted into the core’s pipeline without using the external data bus. • When in debug state, a store-multiple (STM) could be inserted into the instruction pipeline and this would dump the contents of ARM’s registers. 203/213 Debugger (1/2) • Institute of Electronics, National Chiao Tung University • A debugger is software that enables you to make use of a debug agent in order to examine and control the execution of software running on a debug target Different forms of the debug target – early stage of product development, software – prototype, on a PCB including one or more processors – final product • The debugger issues instructions that can – – – – • load software into memory on the target start and stop execution of that software display the contents of memory, registers, and variables allow you to change stored values A debug agent performs the actions requested by the debugger, such as – setting breakpoints – reading from / writing to memory 204/213 Debugger (2/2) Institute of Electronics, National Chiao Tung University Examples of debug agents – – – – – Multi-ICE Embedded ICE ARMulator BATS Angle • Remote Debug Interface (RDI) is an open ARM standard procedural interface between a debugger and the debug agent ARM debugger AxD RDI Remote Debug Interface (RDI) Target (software) Target (hoftware) ARMulator BATS Multi-ICE Angel RDI RDI RDI RDI Remote_A Target emulated in Software Target emulated in Software ARM development board ARM development board 205/213 In Circuit Emulator (ICE) Institute of Electronics, National Chiao Tung University • The processor in the target system is removed and replaced by a connection to an emulator • The emulator may be based around the same processor chip, or a variant with more pins, but it will also incorporate buffers to copy the bus activity to a “trace buffer” and various hardware resources which can watch for particular events, such as execution passing through a breakpoint 206/213 Multi-ICE and Embedded ICE Institute of Electronics, National Chiao Tung University • Multi-ICE and Embedded ICE are JTAG-based debugging systems for ARM processors • They provide the interface between a debugger and an ARM core embedded within an ASIC • It provides – real time address-dependent and data-dependent breakpoints – single stepping – full access to, and control of the ARM core – full access to the ASIC system – full memory access (read and write) – full I/O system access (read and write) 207/213 Basic Debug Requirements Institute of Electronics, National Chiao Tung University • Control of program execution – set watchpoints on interesting data accesses – set breakpoints on interesting instructions – single step through code • Examine and change processor state – read and write register values • Examine and change system state – access to system memory • download initial code 208/213 Debugging with Multi-ICE Institute of Electronics, National Chiao Tung University • • The system being debugged may be the final system Third party protocol converters are also available at http://www.arm.com/DevSupp/ICE_Analyz/ 209/213 ICEBreaker (EmbeddedICE macrocell) • Institute of Electronics, National Chiao Tung University • • ICEBreaker is programmed in a serial fashion using the TAP controller It consists of 2 real-time watchpoint units, together with a control and status register Either watch-point unit can be configured to be a watch-point or a breakpoint DBGRQI EXTERN1 A[31:0] EXTERN0 D[31:0] nOPC nRW TBIT Processor RANGEOUT0 RANGEOUT1 MAS[1:0] ICEBreaker nTRANS DBGACK BREAKPT DBGRQ DBGACKI BREAKPTI DBGEN IFEN ECLK nMREQ SDIN SDOUT TCK nTRST TMS TAP TDI TDO 210/213 Real-Time Trace (1/2) Institute of Electronics, National Chiao Tung University • Debugging uses the breakpoint and single-step to run application code to a given point, and then stop the processor to examine or change memory or register contents, and then step or restart the code • Some bugs occur while the system is running at full clock speed => need non-instrusive trace of instruction flow and data accesses • Using Trace Debug Tool (TDT), you can set up the trace filter facility to collect trace data only during the interrupt routine, and use a trigger to stop tracing 211/213 Real-Time Trace (2/2) Institute of Electronics, National Chiao Tung University ADW and TDT running on the host JTAG Unit ASIC 5-wire JTAG JTAG Port ARM CPU Macrocell Embedded Trace Macrocell Trace Port Trace Port Analyzer • Embedded trace macrocell – monitor the ARM core buses, passed compressed information through the trace port to Trace Port Analyzer (TPA) – the on-chip cell contains the trigger and filter logic • Trace port analyzer – an external device that stores the information from the trace port • Trace debug tool – set up the trigger and filter logic, retrieve the data from the analyzer and reconstruct a historical view of processor activity 212/213 ARM10TDMI (2/2) Institute of Electronics, National Chiao Tung University • Reduce CPI – branch prediction – non-blocking load and store execution – 64-bit data memory => transfer 2 registers in each cycle 213/213...
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