02_ARM_Processor_Core_and_Instruction_Sets

3 address instruction format 48213 conditional

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Unformatted text preview: 32-bit wide; come from registers or specified as literal in the instruction itself • Second operand sent to ALU via barrel shifter • 32-bit result placed in register; long multiply instruction produces 64-bit result • 3-address instruction format 48/213 Conditional Execution Institute of Electronics, National Chiao Tung University • Most instruction sets only allow branches to be executed conditionally. • However by reusing the condition evaluation hardware, ARM effectively increases number of instructions. – all instructions contain a condition field which determines whether the CPU will execute them – non-executed instructions still take up 1 cycle • to allow other stages in the pipeline to complete • This reduces the number of branches which would stall the pipeline – allows very dense in-line code – the time penalty of not executing several conditional instructions is frequently less than overhead of the branch or subroutine call that would otherwise be needed 49/213 Conditional Execution Institute of Electronics, National Chiao Tung University Each of the 16 values causes the instruction to be executed or skipped according to the N, Z, C, V flags in the CPSR 31 28 27 0 cond 50/213 Using and Updating the Condition Field Institute of Electronics, National Chiao Tung University • To execute an instruction conditionally, simply postfix it with the appropriate condition: – for example an add instruction takes the form: • ADD r0,r1,r2 ;r0:=r1+r2 (ADDAL) – to execute this only if the zero flag is set: • ADDEQ r0,r1,r2 ;r0:=r1+r2 iff zero flag is set • By default, data processing operations do not affect the condition flags – with comparison instructions this is the only effect • To cause the condition flags to be updated, the S bit of the instruction needs to be set by postfixing the instruction (and any condition code) with an “S”. – for exammple to add two numbers and set the condition flags: • ADDS r0,r1,r2 ;r0:=r1+r2 and set flags 51/213 Data Processing Instructions Institute of Electronics, National Chiao Tung University • • • • Simple register operands Immediate operands Shifted register operands Multiply 52/213 Simple Register Operands (1/2) Institute of Electronics, National Chiao Tung University • Arithmetic Operations ADD ADC SUB SBC RSB RSC r0,r1,r2 r0,r1,r2 r0,r1,r2 r0,r1,r2 r0,r1,r2 r0,r1,r2 ;r0:=r1+r2 ;r0:=r1+r2+C ;r0:=r1-r2 ;r0:=r1-r2+C-1 ;r0:=r2-r1,reverse subtraction ;r0:=r2-r1+C-1 – by default, data processing operations do not affect the condition flags • Bit-wise Logical Operations AND ORR EOR BIC r0,r1,r2 r0,r1,r2 r0,r1,r2 r0,r1,r2 ;r0:=r1 ;r0:=r1 ;r0:=r1 ;r0:=r1 AND r2 OR r2 XOR r2 AND (NOT r2), bit clear 53/213 Simple Register Operands (2/2) Institute of Electronics, National Chiao Tung University • Register Movement Operations – omit 1st source operand from the format MOV r0,r2 MVN r0,r2 ;r0:=r2 ;r0:=NOT r2, move 1’s complement • Comparison Operations – not produce result; omit the destination from the format – just set the condition code bits (N, Z, C and V) in CPSR CMP CMN TST TEQ r1,r2 r1,r2 r1,r2 r1,r2 ;set ;set ;set ;set cc cc cc cc on on on on r1-r2, r1+r2, r1 AND r1 XOR compare compare negated r2, bit test r2, test equal 54/213 Immediate Operands Institute of Electronics, National Chiao Tung University • Replace the second source operand with an immediate operand, which is a literal constant, preceded by “#” ADD r3,r3,#1 AN...
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