02_ARM_Processor_Core_and_Instruction_Sets

55 institute of electronics national chiao tung

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Unformatted text preview: Architecture Versions (4/5) Institute of Electronics, National Chiao Tung University • Version 5T – introduced recently, a superset of version 4T adding the BLX, CLZand BRK instructions • Version 5TE – add the signal processing instruction set extension 38/213 ARM Architecture Versions (5/5) Institute of Electronics, National Chiao Tung University Core Architecture ARM1 v1 ARM2 v2 ARM2as, ARM3 v2a ARM6, ARM600, ARM610 v3 ARM7, ARM700, ARM710 v3 ARM7TDMI, ARM710T, ARM720T, ARM740T StrongARM, ARM8, ARM810 v4T v4 ARM9TDMI, ARM920T, ARM940T V4T ARM9E-S v5TE ARM10TDMI, ARM1020E v5TE 39/213 Institute of Electronics, National Chiao Tung University 32-bit Instruction Set 40/213 Institute of Electronics, National Chiao Tung University • ARM assembly language program – ARM development board or ARM emulator • ARM instruction set – standard ARM instruction set – a compressed form of the instruction set, a subset of the full ARM instruction set is encoded into 16-bit instructions - Thumb instruction – some ARM cores support instruction set extensions to enhance signal processing capabilities 41/213 Instructions Institute of Electronics, National Chiao Tung University • Data processing instructions • Data transfer instructions • Control flow instructions 42/213 ARM Instruction Set Summary (1/4) Institute of Electronics, National Chiao Tung University Mnemonic Instruction Action ADC Add with carry Rd:=Rn+Op2+Carry ADD Add Rd:=Rn+Op2 AND AND Rd:=Rn AND Op2 B Branch R15:=address BIC Bit Clear Rd:=Rn AND NOT Op2 BL Branch with Link BX Branch and Exchange CDP Coprocessor Data Processing R14:=R15 R15:=address R15:=Rn T bit:=Rn[0] (Coprocessor-specific) CMN Compare Negative CPSR flags:=Rn+Op2 CMP Compare CPSR flags:=Rn-Op2 43/213 ARM Instruction Set Summary (2/4) Institute of Electronics, National Chiao Tung University Mnemonic Instruction Action EOR Exclusive OR Rd:=Rn^Op2 LDC Load Coprocessor from memory (Coprocessor load) LDM Load multiple registers Stack Manipulation (Pop) LDR Load register from memory Rd:=(address) MCR MLA Move CPU register to coprocessor CRn:=rRn{<op>cRm} register Multiply Accumulate Rd:=(Rm*Rs)+Rn MOV Move register or constant MRC MRS Move from coprocessor register to rRn:=cRn{<op>cRm} CPU register Move PSR status/flags to register Rn:=PSR MSR Move register to PSR status/flags Rd:=Op2 PSR:=Rm 44/213 ARM Instruction Set Summary (3/4) Institute of Electronics, National Chiao Tung University Mnemonic Instruction Action MUL Multiply Rd:=Rm*Rs MVN Move negative register Rd:=~Op2 ORR OR Rd:=Rn OR Op2 RSB Reverse Subtract Rd:=Op2-Rn RSC Reverse Subtract with Carry Rd:=Op2-Rn-1+Carry SBC Subtract with Carry Rd:=Rn-Op2-1+Carry STC Store coprocessor register to memory Store Multiple address:=cRn STM Stack manipulation (Push) 45/213 ARM Instruction Set Summary (4/4) Institute of Electronics, National Chiao Tung University Mnemonic Instruction Action STR Store register to memory <address>:=Rd SUB Subtract Rd:=Rn-Op2 SWI Software Interrupt OS call SWP Swap register with memory TEQ Test bitwise equality Rd:=[Rn] [Rn]:=Rm CPSR flags:=Rn EOR Op2 TST Test bits CPSR flags:=Rn AND Op2 46/213 ARM Instruction Set Format Institute of Electronics, National Chiao Tung University 47/213 Data Processing Instructions Institute of Electronics, National Chiao Tung University • Consist of – – – – arithmetic (ADD, SUB, RSB) logical (BIC, AND) compare (CMP, TST) register movement (MOV, MVN) • All operands are...
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This note was uploaded on 08/23/2009 for the course IEE 5016 taught by Professor Tian-sheuanchang during the Spring '05 term at National Chiao Tung University.

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