02_ARM_Processor_Core_and_Instruction_Sets

78213 multiple register data transfer 12 institute of

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Unformatted text preview: s Institute of Electronics, National Chiao Tung University • To allow larger constants to be loaded, the assembler offers a pseudo-instruction: LDR rd,=const • This will either: – produce a MOV or MVN instruction to generate the value (if possible) or – generate a LDR instruction with a PC-relative address to read the constant from a literal pool (Constant data area embedded in the code) • For example LDR r0,=0xFF LDR r0,=0x55555555 ;MOV r0,#0xFF ;LDR r0,[PC,#Imm10] • As this mechanism will always generate the best instruction for a given case, it is the recommended way of loading constants. 78/213 Multiple Register Data Transfer (1/2) • Institute of Electronics, National Chiao Tung University The load and store multiple instructions (LDM/STM) allow between 1 and 16 registers to be transferred to or from memory – order of register transfer cannot be specified, order in the list is insignificant – lowest register number is always transferred to/from lowest memory location accessed • The transferred registers can be either – any subset of the current bank of registers (default) – any subset of the user mode bank of registers when in a privileged mode (postfix instruction with a “^”) • Base register used to determine where memory access should occur – 4 different addressing modes – base register can be optionally updated following the transfer (using “!”) • These instructions are very efficient for – moving blocks of data around memory – saving and restoring context - stack 79/213 Multiple Register Data Transfer (2/2) Institute of Electronics, National Chiao Tung University • Allow any subset (or all, r0 to r15) of the 16 registers to be transferred with a single instruction LDMIA r1,{r0,r2,r5} ;r0:=mem32[r1] ;r2:=mem32[r1+4] ;r5:=mem32[r1+8] 80/213 Stack Processing • Institute of Electronics, National Chiao Tung University • • A stack is usually implemented as a linear data structure which grows up (an ascending stack) or down (a descending stack) memory A stack pointer holds the address of the current top of the stack, either by pointing to the last valid data item pushed onto the stack (a full stack), or by pointing to the vacant slot where the next data item will be placed (an empty stack) ARM multiple register transfer instructions support all four forms of stacks – full ascending: grows up; base register points to the highest address containing a valid item – empty ascending: grows up; base register points to the first empty location above the stack – full descending: grows down; base register points to the lowest address containing a valid data – empty descending: grows down, base register points to the first empty location below the stack 81/213 Block Copy Addressing (1/2) Institute of Electronics, National Chiao Tung University • Addressing modes r9’ r9 r5 r1 r0 101816 100c16 r9’ r5 r1 r0 r9 101816 Ascending Full 100c16 100016 100016 STMIA r9!, {r0, r1, r5} STMIB r9!, {r0, r1, r5} Bef...
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This note was uploaded on 08/23/2009 for the course IEE 5016 taught by Professor Tian-sheuanchang during the Spring '05 term at National Chiao Tung University.

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