02_ARM_Processor_Core_and_Instruction_Sets

02_ARM_Processor_Core_and_Instruction_Sets

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Unformatted text preview: iao Tung University • Most programs operate in user mode. ARM has other privileges operating modes which are used to handle exceptions, supervisor calls (software interrupts), and system mode • More access rights to memory systems and coprocessors • Current operating mode is defined by CPSR[4:0] 9/213 Supervisor Mode Institute of Electronics, National Chiao Tung University • Having some protective privileges • System-level function (transaction with the outside world) can be accessed through specified supervisor calls • Usually implemented by software interrupt (SWI) 10/213 The Registers Institute of Electronics, National Chiao Tung University • ARM has 37 registers, all of which are 32 bits long – – – – 1 dedicated program counter 1 dedicated current program status register 5 dedicated saved program status registers 30 general purpose registers • The current processor mode governs which bank is accessible each mode can access – – – – a particular set of r0-r12 registers a particular r13 (stack pointer, SP) and r14 (link register, LR) the program counter, r15 (PC) the current program status register, CPSR privileged modes (except System) can access – a particular SPSR (saved program status register) 11/213 Register Banking Institute of Electronics, National Chiao Tung University Current Visible Registers r0 User Mode r1 r2 r3 r4 Banked out Registers r5 r6 r7 FIQ IRQ SVC Undef Abort r8 r9 r8 r10 r9 r11 r10 r12 r11 r13 (sp) r12 r14 (lr) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r15 (pc) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) spsr spsr spsr spsr spsr cpsr 12/213 Registers Organization Summary User FIQ IRQ SVC Undef Abort Institute of Electronics, National Chiao Tung University r0 r1 r2 r3 r4 r5 User mode r0-r7, r15, and cpsr r6 r7 User mode r0-r12, r15, and cpsr User mode r0-r12, r15, and cpsr User mode r0-r12, r15, and cpsr User mode r0-r12, r15, and cpsr r8 r8 r9 r9 r10 r10 r11 r11 r12 r12 r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) spsr spsr spsr spsr Thumb state Low registers spsr Thumb state High registers r15 (pc) cpsr Note : System mode uses the User mode reigster set 13/213 Program Counter (r15) Institute of Electronics, National Chiao Tung University • When the processor is executing in ARM state: – all instructions are 32 bits wide – all instructions must be word-aligned – therefore the PC value is stored in bits [31:2] with bits [1:0] undefined (as instruction cannot be halfword or byte aligned) • When the processor is executing in Thumb state: – all instructions are 16 bits wide – all instructions are must be halfword-aligned – therefore the PC value is stored in bits [31:1] with bit [0] undefined (as instruction cannot be byte-aligned) 14/213 Program Status Registers (CPSR) Institute of Electronics, National Chiao Tung University 31 28 27 24 23 NZCVQ f • U 8 ndefined s Condition code flags – – – – • 16 15 N : Negative result from ALU Z : Zero result from ALU C: ALU operation Carried out V : ALU operation oVerflowed Sticky overflow flag – Q flag – architecture 5TE only – indicates if saturation has occurred during certain operations 7 6 5 4 0 mode IFT x c • Interrupt disable bits – I = 1, disables the IRQ – F = 1, disables the FIQ • T Bit – architecture xT only – T = 0, processor in ARM state – T = 1, processor in Thumb state • Mode bits – specify the processor mode...
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This note was uploaded on 08/23/2009 for the course IEE 5016 taught by Professor Tian-sheuanchang during the Spring '05 term at National Chiao Tung University.

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