Cpsr40 to 100112 and cpsr7 to 1 set pc to 0816 and

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Unformatted text preview: half-word boundary by clearing the bottom bit – if Rm[0] is 0, the processor continues executing ARM instructions and begins executing at the address in Rm aligned to a word boundary by clearing Rm[1] • BLX <target address> – call Thumb subroutine from ARM – the H bit (bit 24) is also added into bit 1 of the resulting address, allowing an odd half-word address to be selected for the target instruction which will always be a Thumb instruction 105/213 Example Institute of Electronics, National Chiao Tung University • A call to a Thumb subroutine TSUB CODE32 … BLX TSUB … CODE16 … BX r14 ;call Thumb subroutine ;start of Thumb code ;return to ARM code 106/213 Software Interrupt (SWI) • SWI{<cond>} <24-bit immediate> Institute of Electronics, National Chiao Tung University – used for calls to the operating system and is often called a “supervisor call” – it puts the processor into supervisor mode and begins executing instruction from address 0x08 • Save the address of the instruction after SWI in r14_svc • Save the CPSR in SPSR_svc • Enter supervisor mode and disable IRQs by setting CPSR[4:0] to 100112 and CPSR[7] to 1 • Set PC to 0816 and begin executing the instruction there – the 24-bit immediate does not influence the operation of the instruction but may be interpreted by the system code 107/213 Examples • Output the character ‘A’ Institute of Electronics, National Chiao Tung University MOV SWI r0,#’A’ SWI_WriteC • Finish executing the user program and return to the monitor SWI SWI_Exit • A subroutine to output a text string STROUT BL STROUT = “Hello World”,&0a,&0d,0 … LDRB r0,[r14],#1 ;get character CMP r0,#0 ;check for end marker SWINE SWI_WriteC ;if not end, print BNE STROUT ; … , loop ADD r14,#3 ;align to next word BIC r14,#3 MOV PC,r14 ;return 108/213 Coprocessor Instructions Institute of Electronics, National Chiao Tung University • Extend the instruction set through the addition of coprocessors – System Coprocessor: control on-chip function such as cache and memory management unit – Floating-point Coprocessor – Application-Specific Coprocessor • Coprocessors have their own private register sets and their state is controlled by instructions that mirror the instructions that control ARM registers 109/213 Coprocessor Data Operations • CDP{<cond>}<CP#>,<Cop1>,CRd,CRn,CRm{,<Cop2>} Institute of Electronics, National Chiao Tung University 31 28 27 cond 1110 24 23 2019 Cop1 CRn 16 15 12 11 CRd 87 54 3 0 CP# Cop2 0 CRm • Use to control internal operations on data in coprocessor registers • CP# identifies the coprocessor number • Cop1, Cop2 operation • Examples CDP P2,3,C0,C1,C2 CDPEQ P3,6,C1,C5,C7,4 110/213 Coprocessor Data Transfers • Pre-indexed form Institute of Electronics, National Chiao Tung University LDC|STC{<cond>}{L}<CP#>,CRd,[Rn,<offset>]{!} • Post-indexed form LDC|STC{<cond>}{L}<CP#>,CRd,[Rn],<offset> – L flag, if present, selects the long data type – <offset> is # +/-<8-bit immediate> 31 28 27 25 23 21 24 22 2019 cond 1110 P U N WL CRn 16 15 12 11 CRd CP# 87 0 8-bit offset source/destination register base register load/store write-back (auto-index) data size (coprocessor dependent) up/down pre-/post-index – the number of words transferred is controlled by the coprocessor – address calculated within ARM; number of words transferred controlled...
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This note was uploaded on 08/23/2009 for the course IEE 5016 taught by Professor Tian-sheuanchang during the Spring '05 term at National Chiao Tung University.

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