02_ARM_Processor_Core_and_Instruction_Sets

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Unformatted text preview: higher priority input signals are level-sensitive and maskable • May include Direct Memory Access (DMA) hardware 30/213 ARM Exceptions Institute of Electronics, National Chiao Tung University • Supports interrupts, traps, supervisor calls • When an exception occurs, the ARM: – copies CPSR into SPSR_<mode> – sets appropriate CPSR bits • if core currently in Thumb state then ARM state is entered • mode field bits • interrupt disable bits (if appropriate) 0x1C FIQ 0x18 IRQ 0x14 (Reserved) 0x10 Data Abort 0x0C Prefetch Abort – stores the return address in LR_<mode> – set pc to vector address 0x08 Software Interrupt 0x04 Undefined Instruction 0x00 Reset • To return, exception handler needs to: – restore CPSR from SPSR_<mode> – restore PC from LR_<mode> Vector Table Vector table can be at 0xffff0000 on ARM720T and on ARM9/10 family devices This can only be done in ARM state 31/213 ARM Exceptions Institute of Electronics, National Chiao Tung University • Exception handler use r13_<mode> which will normally have been initialized to point to a dedicated stack in memory, to save some user registers for use as work registers 32/213 ARM Processor Cores Institute of Electronics, National Chiao Tung University • ARM Processor core + cache + MMU →ARM CPU cores • ARM6 → ARM7 (3V operation, 50-100MHz for .25µ or .18 µ) T : Thumb 16-bit compressed instruction set D : on-chip Debug support, enabling the processor to halt in response to a debug request M : enhanced Multiplier, 64-bit result I : embedded ICE hardware, give on-chip breakpoint and watchpoint support 33/213 ARM Processor Cores Institute of Electronics, National Chiao Tung University • ARM 8 → ARM 9 → ARM 10 • ARM 9 – 5-stage pipeline (130 MHz or 200MHz) – using separate instruction and data memory ports • ARM 10 (1998. Oct.) – high performance, 300 MHz – multimedia digital consumer applications – optional vector floating-point unit 34/213 ARM Architecture Versions (1/5) Institute of Electronics, National Chiao Tung University • Version 1 – the first ARM processor, developed at Acorn Computers Limited 1983-1985 – 26-bit addressing, no multiply or coprocessor support • Version 2 – sold in volume in the Acorn Archimedes – 26-bit addressing, including 32-bit result multiply and coprocessor • Version 2a – coprocessor 15 as the system control coprocessor to manage cache – add the atomic load store (SWP) instruction 35/213 ARM Architecture Versions (2/5) Institute of Electronics, National Chiao Tung University • Version 3 – first ARM processor designed by ARM Limited (1990) – ARM6 (macro cell) ARM60 (stand-alone processor) ARM600 (an integrated CPU with on-chip cache, MMU, write buffer) ARM610 (used in Apple Newton) – 32-bit addressing, separate CPSR and SPSRs – add the undefined and abort modes to allow coprocessor emulation and virtual memory support in supervisor mode • Version 3M – introduce the signed and unsigned multiply and multiplyaccumulate instructions that generate the full 64-bit result 36/213 ARM Architecture Versions (3/5) Institute of Electronics, National Chiao Tung University • Version 4 – add the signed, unsigned half-word and signed byte load and store instructions – reserve some of SWI space for architecturally defined operations – system mode is introduced • Version 4T – 16-bit Thumb compressed form of the instruction set is introduced 37/213 ARM...
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This note was uploaded on 08/23/2009 for the course IEE 5016 taught by Professor Tian-sheuanchang during the Spring '05 term at National Chiao Tung University.

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