02_ARM_Processor_Core_and_Instruction_Sets

Electronics national chiao tung university when the

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Unformatted text preview: S’ signifies when the destination register is the PC 21/213 Exception Return (3/3) Institute of Electronics, National Chiao Tung University • When the return address has been saved onto a stack LDMFD r13!,{r0-r3,PC}^ ;restore and return – ‘^’ indicates that this is a special form of the instruction the CPSR is restored at the same time that the PC is loaded from memory, which will always be the last item transferred from memory since the registers are loaded in increasing order 22/213 Exception Priorities Institute of Electronics, National Chiao Tung University • Priority order 1. 2. 3. 4. 5. 6. reset (highest priority) data abort FIQ IRQ prefetch abort SWI, undefined instruction 23/213 Memory Organization bit 31 Institute of Electronics, National Chiao Tung University 23 22 bit 31 bit 0 21 20 20 18 17 16 word16 15 14 13 12 half-word14 half-word12 11 10 9 8 word8 7 6 5 4 byte6 half-word4 3 2 1 0 byte3 byte2 byte1 byte0 22 23 16 19 (a) Little-endian memory organization 21 bit 0 byte address 17 18 19 word16 15 12 13 14 half-word12 half-word14 8 9 10 11 word8 4 5 6 7 byte5 half-word6 0 1 2 3 byte0 byte1 byte2 byte3 byte address (b) Big-endian memory organization • Word, half-word alignment (xxxxoo or xxxxxo) • ARM can be set up to access data in either littleendian or big-endian format 24/213 Features of the ARM Instruction Set Institute of Electronics, National Chiao Tung University • Load-store architecture process values which are in registers load, store instructions for memory data accesses • • • • • 3-address data processing instructions Conditional execution of every instruction Load and store multiple registers Shift, ALU operation in a single instruction Open instruction set extension through the coprocessor instruction • Very dense 16-bit compressed instruction set (Thumb) 25/213 Coprocessors Institute of Electronics, National Chiao Tung University Handshaking signals ARM core F DE Coprocessor X F DE Coprocessor Y F DE Databus • Up to 16 coprocessor can be defined • Expands the ARM instruction set • ARM uses them for “internal functions” so as not to enforce a particular memory map (eg cp15 is the ARM cache controller) • Usually better for system designers to use memory mapped peripherals - easier to implement 26/213 Thumb Institute of Electronics, National Chiao Tung University • Thumb is a 16-bit instruction set – optimized for code density from C code – improved performance from narrow memory – subset of the fumctionality of the ARM instruction set • Core has two execution states – ARM and Thumb 31 – switch between them using BX instruction 0 ADDS r2,r2,#1 15 ADD r2,#1 32-bit ARM instruction For most instruction generated by compiler: • Conditional execution is not used • Source and destination registers identical • Only Low registers used • Constants are of limited size 0 • Inline barrel shifter not used 16-bit Thumb instruction 27/213 Average Thumb Code Sizes Institute of Electronics, National Chiao Tung University 28/213 ARM and Thumb Performace Institute of Electronics, National Chiao Tung University 29/213 I/O System Institute of Electronics, National Chiao Tung University • ARM handles input/output peripherals as memory-mapped with interrupt support • Internal registers in I/O devices as addressable locations within ARM’s memory map read and written using load-store instructions • Interrupt by normal interrupt (IRQ) or fast interrupt (FIQ)...
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This note was uploaded on 08/23/2009 for the course IEE 5016 taught by Professor Tian-sheuanchang during the Spring '05 term at National Chiao Tung University.

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