02_ARM_Processor_Core_and_Instruction_Sets

Link bl subroutine implemented as a pair of

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Unformatted text preview: ed conditionally) • Many Thumb data processing instructions use a 2-address format, i.e. the destination register is the same as one of the source registers (ARM data processing instructions, with the exception of the 64-bit multiplies, use a 3-address format) • Thumb instruction formats are less regular than ARM instruction formats => dense encoding 120/213 Register Access in Thumb Institute of Electronics, National Chiao Tung University • Not all registers are directly accessible in Thumb • Low register r0~r7: fully accessible • High register r8~r12: only accessible with MOV, ADD, CMP; only CMP sets the condition code flags • SP(stack pointer), LR(link register) & PC(program counter): limited accessibility, certain instructions have implicit access to these • CPSR: only indirect access • SPSR: no access 121/213 Thumb Accessible Registers Institute of Electronics, National Chiao Tung University 122/213 Branches • Institute of Electronics, National Chiao Tung University Thumb defines three PC-relative branch instructions, each of which have different offset ranges – Offset depends upon the number of available bits • Conditional Branches – B<cond> label – 8-bit offset: range of -128 to 127 instructions (+/-256 bytes) – Only conditional Thumb instructions • Unconditional Branches – B label – 11-bit offset: range of -1024 to 1023 instructions (+/- 2Kbytes) • Long Branches with Link – BL subroutine – Implemented as a pair of instructions – 22-bit offset: range of -2097152 to 2097151 instructions (+/- 4Mbytes) 123/213 Data Processing Instructions Institute of Electronics, National Chiao Tung University • Subset of the ARM data processing instructions • Separate shift instructions (e.g. LSL, ASR, LSR, ROR) LSL Rd,Rs,#Imm5 ASR Rd,Rs ;Rd:=Rs <shift> #Imm5 ;Rd:=Rd <shift> Rs • Two operands for data processing instructions – act on low registers BIC Rd,Rs ADD Rd,#Imm8 ;Rd:=Rd AND NOT Rs ;Rd:=Rd+#Imm8 – also three operand forms of add, subtract and shifts ADD Rd,Rs,#Imm3 ;Rd:=Rs+#Imm3 • Condition code always set by low register operations 124/213 Load or Store Register • Two pre-indexed addressing modes Institute of Electronics, National Chiao Tung University – base register+offset register – base register+5-bit offset, where offset scaled by • 4 for word accesses (range of 0-124 bytes / 0-31 words) – STR Rd,[Rb,#Imm7] • 2 for halfword accesses (range of 0-62 bytes / 0-31 halfwords) – LDRH Rd,[Rb,#Imm6] • 1 for byte accesses (range of 0-31 bytes) – LDRB Rd,[Rb,#Imm5] • Special forms: – load with PC as base with 1Kbyte immediate offset (word aligned) • used for loading a value from a literal pool – load and store with SP as base with 1Kbyte immediate offset (word aligned) • used for accessing local variables on the stack 125/213 Block Data Transfers Institute of Electronics, National Chiao Tung University • Memory copy, incrementing base pointer after transfer – STMIA Rb!, {Low Reg list} – LDMIA Rb!, {Low Reg list} • Full descending stack operations – – – – PUSH {Low Reg list} PUSH {Low Reg list, LR} POP {Low Re...
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