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Unformatted text preview: D r8,r7,#&FF ;r3:=r3+1
;r8:=r7[7:0], &:hexadecimal • Immediate = (0~255)*22n
where n is 015 4bit value 55/213 Shifted Register Operands
Institute of Electronics, National Chiao Tung University • ADD r3,r2,r1,LSL#3
;r3:=r2+8*r1
– a single instruction executed in a
single cycle •
• LSL: Logical shift left by 0 to 31
places, 0 filled at the lsb end
LSR, ASL(Arithmetic Shift Left),
ASR, ROR(Rotate Right),
RRX(Rotate Right eXtended by 1
place) • ADD r5,r5,r3,LSL r2
;r5:=r5+r3*2r2
• MOV r12,r4,ROR r3
;r12:=r4
rotated right by value of r3 56/213 Using the Barrel Shifter: the 2nd Operand
Institute of Electronics, National Chiao Tung University Operand
1 Operand
2 • Register, optionally with shift operation
applied.
– Shift value can be either:
• 5bit unsigned integer
• Specified in bottom byte of another
register Barrel
Shifter – Used for multiplication by constant • ALU
Result Immediate value
– 8bit number, with a range of 0255
• Rotated right through even number of
positions – Allows increased range of 32bit
constants to be loaded directly into
registers 57/213 Multiply
Institute of Electronics, National Chiao Tung University MUL r4,r3,r2 ;r4:=(r3*r2)[31:0] • MultiplyAccumulate
MLA r4,r3,r2,r1 ;r4:=(r3*r2+r1)[31:0] 58/213 Multiplication by a Constant
Institute of Electronics, National Chiao Tung University • Multiplication by a constant equals to a ((power of 2) +/ 1)
can be done in a single cycle
•
• – Using MOV, ADD or RSBs with an inline shift
Example: r0=r1*5
Example: r0=r1+(r1*4)
ADD r0,r1,r1,LSL #2 • Can combine several instructions to carry out other
multiplies
•
•
• Example: r2=r3*119
Example: r2=r3*17*7
Example: r2=r3*(16+1)*(81)
ADD r2,r3,r3,LSL #4 ;r2:=r3*17
RSB r2,r2,r2,LSL #3 ;r2:=r2*7
59/213 Data Processing Instructions (1/3)
Institute of Electronics, National Chiao Tung University • <op>{<cond>}{S} Rd,Rn,#<32bit immediate>
• <op>{<cond>}{S} Rd,Rn,Rm,{<shift>}
– omit Rn when the instruction is monadic (MOV, MVN)
– omit Rd when the instruction is a comparison, producing only
condition code outputs (CMP, CMN, TST, TEQ)
– <shift> specifies the shift type (LSL, LSR, ASL, ASR, ROR or RRX)
and in all cases but RRX, the shift amount which may be a 5bit
immediate (# < # shift>) or a register Rs • 3address format
– 2 source operands and 1 destination register
– one source is always a register, the second may be a register, a
shifted register or an immediate value 60/213 Data Processing Instructions (2/3)
Institute of Electronics, National Chiao Tung University 61/213 Data Processing Instructions (3/3)
•
Institute of Electronics, National Chiao Tung University Allows direct control of whether or not the condition codes are affected
by S bit (condition code unchanged when S=0)
N=1 if the result is negative; 0 otherwise
(i.e. N=bit 31 of the result)
Z=1 if the result is zero; 0 otherwise
C= carry out from the ALU when ADD, ADC, SUB, SBC, RSB, RSC, CMP,
CMN; carry out from the shifter
V=1 if overflow from bit 30 to bit 31; 0 if no overflow
(V is preserved in nonarithmetic operations) •
• PC may be used as a source operand (address of the instruction plus
8) except when a registerspecified shift amount is used
PC may be specified as the destination register, the instruction is a
form of branch (return from a subroutine) 62/213 Examples
Institute of Electronics, National Chiao Tung University •
• AD...
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This note was uploaded on 08/23/2009 for the course IEE 5016 taught by Professor Tiansheuanchang during the Spring '05 term at National Chiao Tung University.
 Spring '05
 TianSheuanChang

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