02_ARM_Processor_Core_and_Instruction_Sets

Macrocells institute of electronics national chiao

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Unformatted text preview: ttle-endian 151/213 ARM7TDMI Interface Signals (4/4) Institute of Electronics, National Chiao Tung University • Interrupt – \fiq, fast interrupt request, higher priority – \irq, normal interrupt request – isync, allow the interrupt synchronizer to be passed • Initialization – \reset, starts the processor from a known state, executing from address 0000000016 • ARM7TDMI characteristics 152/213 External Address Generation Institute of Electronics, National Chiao Tung University 153/213 Memory Access Institute of Electronics, National Chiao Tung University 154/213 ARM Memory Interface Institute of Electronics, National Chiao Tung University 155/213 Instruction Execution Cycles (1/2) Institute of Electronics, National Chiao Tung University Instruction Qualifier Cycle count Any unexecuted Condition codes fail +S D ata processing Single-cycle +S D ata processing Register-specified shift +I +S D ata processing R15 destination +N +2S D ata processing R15, register-specified shift +I +N +2S MUL +(m)I +S MLA +I +(m)I +S MULL +(m)I +I +S MLAL +I +(m)I +I +S B, BL +N +2S LDR Non-R15 destination +N +I +S 156/213 Instruction Execution Cycles (2/2) Institute of Electronics, National Chiao Tung University Instruction Qualifier Cycle count LDR R15 destination +N +I +N +2S STR +N +N SWP +N +N +I +S LDM Non-R15 destination +N +(n-1)S +I +S LDM R15 destination +N +(n-1)S +I +N +2S STM +N +(n-1)S +I +N MSR, MRS +S SWI, trap +N +2S CDP +(b)I +S MCR +(b)I +C +N MRC +(b)I +C +I +S LDC, STC +(b)I +N +(n-1)S +N 157/213 Effect of T bit Institute of Electronics, National Chiao Tung University 158/213 Cached ARM7TDMI Macrocells Institute of Electronics, National Chiao Tung University 159/213 ARM 8 • Higher performance than ARM7 Institute of Electronics, National Chiao Tung University – by increasing the clock rate – by reducing the CPI • higher memory bandwidth, 64-bit wide memory • Separate memories for instruction and data accesses • • ARM8 ARM9TDMI ARM10TDMI Core Organization – the prefetch unit is responsible for fetching instructions from memory and buffering them (exploiting the double bandwidth memory) – it is also responsible for branch prediction and use static prediction based on the branch prediction (backward: predicted ‘taken’, forward: predicted ‘not taken’) 160/213 Pipeline Organization Institute of Electronics, National Chiao Tung University • 5-stage, prefetch unit occupies the 1st stage, integer unit occupies the remainder (1) Instruction prefetch (2) Instruction decode and register read (3) Execute (shift and ALU) (4) Data memory access (5) Write back results 161/213 Integer Unit Organization Institute of Electronics, National Chiao Tung University 162/213 ARM9TDMI Institute of Electronics, National Chiao Tung University • Harvard architecture – increases available memory bandwidth • instruction memory interface • data memory interface – simultaneous accesses to instruction and data memory can be achieved • 5-stage pipeline • Changes implemented to – improve CPI to ~1.5 – improve maximum clock frequency 163/213 ARM9TDMI Organization Institute of Electronics, National Chiao Tung University 164/213 ARM9TDMI Pipeline Operations (1/2) Institute of Electronics, National Chiao Tung University • Not sufficient slack time to translate Thumb instructions into ARM instructions and then decode, instead the hardware decode both ARM and Thumb instructions directly 165/213 ARM9T...
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