02_ARM_Processor_Core_and_Instruction_Sets

National chiao tung university 1 2 3 4 5 fetch add

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Unformatted text preview: nter Data Registers – Hold data passing to and from memory • Instruction Decoder and Control 134/213 Data Processing Instructions Institute of Electronics, National Chiao Tung University • All Operations take place in a single clock cycle 135/213 3-Stage Pipeline (1/2) Institute of Electronics, National Chiao Tung University 1 2 3 fetch decode execute fetch decode execute fetch decode execute instruction • Fetch time – the instruction is fetched from memory and placed in the instruction pipeline • Decode – the instruction is decoded and the datapath control signals prepared for the next cycle • Execute – the register bank is read, an operand shifted, the ALU result generated and written back into a destination register 136/213 3-Stage Pipeline (2/2) Institute of Electronics, National Chiao Tung University • At any time slice, 3 different instructions may occupy each of these stages, so the hardware in each stage has to be capable of independent operations • When the processor is executing data processing instructions, the latency = 3 cycles and the throughput = 1 instruction/cycle • When accessing r15 (PC), r15=address of current instruction + 8 137/213 Data Transfer Instructions Institute of Electronics, National Chiao Tung University • • Computes a memory address similar to a data processing instruction Load instruction follow a similar pattern except that the data from memory only gets as far as the ‘data in’ register on the 2nd cycle and a third cycle is needed to transfer the data from there to the destination register 138/213 Multi-cycle Instruction Institute of Electronics, National Chiao Tung University 1 2 3 4 5 fetch ADD decode execute fetch STR decode calc. addr. fetch ADD data xfer decode fetch ADD execute decode fetch ADD execute decode execute instruction time • • • Memory access (fetch, data transfer) in every cycle Datapath used in every cycle (execute, address calculation, data transfer) Decode logic generates the control signals for the data path use in next cycle (decode, address calculation) 139/213 Branch Instructions Institute of Electronics, National Chiao Tung University • The third cycle, which is required to complete the pipeline refilling, is also used to make a small correction to the value stored in the link register in order that it points directly at the instruction which follows the branch 140/213 Branch Pipeline Example Institute of Electronics, National Chiao Tung University Cycle address 1 2 3 decode execute linkret adjust fetch decode fetch decode fetch 4 5 opeation 0x8000 BL fetch 0x8004 X 0x8008 XX 0x8FEC ADD 0x8FF0 SUB fetch 0x8FF4 MOV execute decode execute fetch decode fetch Breaking the pipeline Note that the core is executing in ARM state 141/213 Interrupt Pipeline Example Institute of Electronics, National Chiao Tung University IRQ 1 Cycle address 2 3 4 execute IRQ linkret 5 6 7 8 adjust opeation 0x8000 ADD fetch 0x8004 SUB 0x8008 MOV decode execute fetch decode IRQ 0x800C X F00) 0x001C B(to 0xA 0x0018 XX 0x0020 XXX 0xAF00 STMFD 0xAF04 MOV 0xAF08 LDR fetch fetch fetch decode execute fetch decode fetch fetch decode execute fetch decode fetch IRQ interrupt m inim latency = 7 cycyles um 142/213 5-Stage Pipelined ARM Organization Institute of Electronics, National Chiao Tung University • Tprog=Ninst*CPI*cycle_time – Ninst, compiler dependent – CPI, hazard => pipeline stalls – cycle_time, frequency • Separate instruction and data memories =&gt...
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This note was uploaded on 08/23/2009 for the course IEE 5016 taught by Professor Tian-sheuanchang during the Spring '05 term at National Chiao Tung University.

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