02_ARM_Processor_Core_and_Instruction_Sets

Overview architecture v5t institute of electronics

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Unformatted text preview: DMI Datapath (1/2) Institute of Electronics, National Chiao Tung University 166/213 ARM9TDMI Datapath (2/2) Institute of Electronics, National Chiao Tung University 167/213 LDR Interlock Institute of Electronics, National Chiao Tung University 168/213 Optimal Pipelining Institute of Electronics, National Chiao Tung University 169/213 LDM Interlock (1/2) Institute of Electronics, National Chiao Tung University 170/213 LDM Interlock (2/2) Institute of Electronics, National Chiao Tung University 171/213 Example ARM9TDMI System Institute of Electronics, National Chiao Tung University 172/213 Cached ARM9TDMI Macrocell Institute of Electronics, National Chiao Tung University 173/213 ARM9TDMI Pipeline Operations (2/2) Institute of Electronics, National Chiao Tung University • Coprocessor support – coprocessors: floating-point, digital signal processing, special-purpose hardware accelerator • On-chip debug – additional features compared to ARM7TDMI • hardware single stepping • breakpoint can be set on exceptions • ARM9TDMI characteristics 174/213 ARM9E-S Family Overview • ARM9E is based on an ARM9TDMI with the following extensions Institute of Electronics, National Chiao Tung University – – – – – – • Architecture v5TE ARM946E-S – – – – – • single cycle 32*16 multiplier implementation EmbeddedICE Logic RT improved ARM/Thumb interworking new 32*16 and 16*16 multiply instructions new count leading zeros instruction new saturated maths instructions ARM9E-S core instruction and data caches, selectable sizes instruction and data RAMs, selectable sizes protection unit AHB bus interface ARM966E-S – similar to ARM946-S, but with no cache 175/213 ARM1020T Overview • Architecture v5T Institute of Electronics, National Chiao Tung University – ARM1020E will be v5TE • • • • CPI ~ 1.3 6-stage pipeline Static branch prediction 32KB instruction and 32KB data caches – ‘hit under miss’ support • • • • 64 bits per cycle LDM/STM operations EmbeddedICE Logic RT-II Support for new VFPv1 architecture ARM10200 test chip – – – – ARM1020T VFP10 SDRAM memory interface PLL 176/213 ARM10TDMI (1/2) Institute of Electronics, National Chiao Tung University • Current high-end ARM processor core • Performance on the same IC process ARM10TDMI ARM9TDMI *2 ARM7TDMI *2 • 300MHz, 0.25uM CMOS • Increase clock rate 177/213 Institute of Electronics, National Chiao Tung University Software Development 178/213 Institute of Electronics, National Chiao Tung University • ARM software development - ADS • ARM system development - ICE and trace • ARM-based SoC development – modeling, tools, design flow C source C libraries asm source C compiler assembler .aof object libraries linker .aif system model debug ARMsd ARMulator development board 179/213 ARM Development Suite (ADS), ARM Software Development Toolkit (SDT) (1/3) Institute of Electronics, National Chiao Tung University • Develop and debug C, C++ or assembly language program • armcc ARM C compiler armcpp ARM C++ compiler tcc Thumb C compiler tcpp Thumb C++ compiler armasm ARM and Thumb assembler armlink ARM linker - combine the contents of one or more object files with selected parts of one or more object libraries to produce an executable program - ARM linker creates ELF executable images armsd ARM and Thumb symbolic debugger - can single-step through C or assembly language sources, set break-points and watch-points, and examine program...
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This note was uploaded on 08/23/2009 for the course IEE 5016 taught by Professor Tian-sheuanchang during the Spring '05 term at National Chiao Tung University.

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