02_ARM_Processor_Core_and_Instruction_Sets

Scan 12 institute of electronics national chiao tung

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Unformatted text preview: ute of Electronics, National Chiao Tung University • A motherboard with some extensions to support the development of applications Provide core modules, logic modules (Xilinx Virtex FPGA), OS, input/output resources, bus arbitration, interrupt handling Logic Module Connectors • System Controller FPGA PCI Host Bridge FLASH Standard PCI Slot SRAM Standard PCI Slot GPIO Standard PCI Slot Boot ROM PCI PCI Bridge Compact PCI 193/213 Rapid Silicon Prototyping (VLSI Tech. Inc.) • Specially developed reference chips + off-chip extensions Institute of Electronics, National Chiao Tung University 194/213 ARMulator (1/2) Institute of Electronics, National Chiao Tung University • ARMulator is a collection of programs that emulate the instruction sets and architecture of various ARM processors (It is an instruction set simulator) • ARMulator is suited to software development and benchmarking ARM-targeted software. It models the instruction set and counts cycles. • ARMulator supports a C library to allow complete C programs to run on the simulated system • To run software on ARMulator, through ARM symbolic debugger or ARM GUI debuggers, AxD 195/213 ARMulator (2/2) • It includes Institute of Electronics, National Chiao Tung University – processor core models which can emulate any ARM core – a memory interface which allows the characteristics of the target memory system to be modeled – a coprocessor interface that supports custom coprocessor models – an OS interface that allows individual system calls to be handled • • • The processor core model incorporates the remote debug interface, so the processor and the system state are visible from the ARM symbolic debugger ARMulator => a cycle accurate model of a system including a cache, MMU, physical memory, peripheral devices, OS, software Once the design is OK, hardware -> design or synthesis by CAD software -> still use ARMulator model, but instruction accurate 196/213 JTAG Boundary Scan (1/2) • Institute of Electronics, National Chiao Tung University IEEE 1149, Standard Test Access Port and Boundary Scan Architecture or called JTAG boundary scan (by Joint Test Action Group) 197/213 JTAG Boundary Scan (2/2) Institute of Electronics, National Chiao Tung University • Test signals – \TRST: – TCK: – TMS: – TDI: – TDO: a test reset input test clock which controls the timing of the test interface independently from any system clock test mode select which controls the operation of the test interface state machine test data input line test data output line • TAP controller (Test Access Port) A state machine whose state transitions are controlled by TMS 198/213 TAP Controller (1/2) test logic reset Institute of Electronics, National Chiao Tung University run test/idle select DR scan select IR scan capture DR capture IR shift DR shift IR exit1 DR exit1 IR pause DR pause IR exit2 DR exit2 IR update DR update IR TMS=0 TMS=1 199/213 TAP Controller (2/2) Institute of Electronics, National Chiao Tung University • Test instr...
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