02_ARM_Processor_Core_and_Instruction_Sets

University each privileged mode except system mode

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: 15/213 SPSRs Institute of Electronics, National Chiao Tung University • Each privileged mode (except system mode) has associated with it a Save Program Status Register, or SPSR • This SPSR is used to save the state of CPSR (Current Program Status Register) when the privileged mode is entered in order that the user state can be fully restored when the user process is resumed • Often the SPSR may be untouched from the time the privileged mode is entered to the time it is used to restore the CPSR, but if the privileged supervisor calls to itself) then the SPSR must be copied into a general register and saved 16/213 Exceptions Institute of Electronics, National Chiao Tung University • • Exceptions are usually used to handle unexpected events which arise during the execution of a program, such as interrupts or memory faults, also cover software interrupts, undefined instruction traps, and the system reset Three groups : 1. generated as the direct effect of executing an instruction software interrupts, undefined instructions, prefetch abort (memory fault) 2. generated as the side-effect of an instruction data aborts 3. generated externally reset, IRQ, FIQ 17/213 Exception Entry (1/2) Institute of Electronics, National Chiao Tung University • When an exception arises, ARM completes the current instruction as best it can (except that reset exception terminates the current instruction immediately) and then departs from the current instruction sequence to handle the exception which starts from a specific location (exception vector) • Processor performs the following sequence – change to the operating mode corresponding to the particular exception – save the address of the instruction following the exception entry instruction in r14 of the new mode – save the old value of CPSR in the SPSR of the new mode – disable IRQs by setting bit of the CPSR, and if the exception is a fast interrupt, disable further faster interrupt by setting bit of the CPSR 18/213 Exception Entry (2/2) – force the PC to begin executing at the relevant vector address Institute of Electronics, National Chiao Tung University Exception Mode Vector address Reset SVC 0x00000000 Undefined instruction UND 0x00000004 Software interrupt (SWI) SVC 0x00000008 Prefetch abort (instruction fetch memory fault) Abort 0x0000000C Data abort (data access memory fault) Abort 0x00000010 IRQ (normal interrupt) IRQ 0x00000018 FIQ (fast interrupt) FIQ 0x0000001C • Normally the vector address contains a branch to the relevant routine, though the FIQ code can start immediately • Two banked registers in each of the privilege modes are used to hold the return address and stack pointer 19/213 Exception Return (1/3) Institute of Electronics, National Chiao Tung University • Once the exception has been handled, the user task is normally resumed • The sequence is – any modified user registers must be restored from the handler’stack – CPSR must be restored from the appropriate SPSR – PC must be changed back to the relevant instruction address • The last two steps happen atomically as part of a single instruction 20/213 Exception Return (2/3) Institute of Electronics, National Chiao Tung University • When the return address has been kept in the banked r14 – to return from a SWI or undefined instruction trap MOVS PC,r14 – to return from an IRQ, FIQ or prefetch abort SUBS PC,r14,#4 – To return from a data abort to retry the data access SUBS PC,r14,#8 – ‘...
View Full Document

This note was uploaded on 08/23/2009 for the course IEE 5016 taught by Professor Tian-sheuanchang during the Spring '05 term at National Chiao Tung University.

Ask a homework question - tutors are online