G access to cpsr to enabledisable interrupts to change

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: g list} POP {Low Reg list, PC} • The optional addition of the LR/PC provides support for subroutine entry/exit. 126/213 Miscellaneous Institute of Electronics, National Chiao Tung University • Thumb SWI instruction format – same effect as ARM, but SWI number limited to 0~255 – syntax: • SWI <SWI number> 15 1 8 1 0 1 1 1 1 1 7 0 SWI number • Indirect access to CPSR and no access to SPSR, so no MRS or MSR instructions • No coprocessor instruction space 127/213 Thumb Instruction Entry and Exit Institute of Electronics, National Chiao Tung University • T bit, bit 5 of CPSR – if T=1, the processor interprets the instruction stream as 16-bit Thumb instruction – if T=0, the processor interprets it as standard ARM instructions • Thumb Entry – ARM cores startup, after reset, executing ARM instructions – executing a Branch and Exchange instruction (BX) • set the T bit if the bottom bit of the specified register was set • switch the PC to the address given in the remainder of the register • Thumb Exit – executing a Thumb BX instruction 128/213 The Need for Interworking Institute of Electronics, National Chiao Tung University • The code density of Thumb and its performance from narrow memory make it ideal for the bulk of C code in many systems. However there is still a need to change between ARM and Thumb state within most applications: – ARM code provides better performance from wide memory • therefore ideal for speed-critical parts of an application – some functions can only be performed with ARM instructions, e.g. • access to CPSR (to enable/disable interrupts & to change mode) • access to coprocessors – exception Handling • ARM state is automatically entered for exception handling, but system specification may require usage of Thumb code for main handler – simple standalone Thumb programs will also need an ARM assembler header to change state and call the Thumb routine 129/213 Interworking Instructions Institute of Electronics, National Chiao Tung University • Interworking is achieved using the Branch Exchange instructions – in Thumb state BX Rn – in ARM state (on Thumb-aware cores only) BX<condition> Rn where Rn can be any registers (r0 to r15) • This performs a branch to an absolute address in 4GB address space by copying Rn to the program counter • Bit 0 of Rn specifies the state to change to 130/213 Switching between States Institute of Electronics, National Chiao Tung University 31 1 0 Rn BX 31 ARM/Thumb Selection 0- ARM State 1- Thumb State 1 0 0 Destination Address 131/213 Example Institute of Electronics, National Chiao Tung University ;start off in ARM state CODE32 ADR r0,Into_Thumb+1 ;generate branch target ;address & set bit 0, ;hence arrive Thumb state BX r0 ;branch exchange to Thumb … CODE16 ;assemble subsequent as ;Thumb Into_Thumb … ADR r5,Back_to_ARM ;generate branch target to ;word-aligned address, ;hence bit 0 is cleared. BX r5 ;branch exchange to ARM … CODE32 ;assemble subsequent as ;ARM Back_to_ARM … 132/213 Institute of Electronics, National Chiao Tung University ARM Processor Core 133/213 3-Stage Pipeline ARM Organization Institute of Electronics, National Chiao Tung University • Register Bank – 2 read ports, 1write ports, access any register – 1 additional read port, 1 additional write port for r15 (PC) • Barrel Shifter – Shift or rotate the operand by any number of bits • • • ALU Address register and increme...
View Full Document

This note was uploaded on 08/23/2009 for the course IEE 5016 taught by Professor Tian-sheuanchang during the Spring '05 term at National Chiao Tung University.

Ask a homework question - tutors are online