02_ARM_Processor_Core_and_Instruction_Sets

Instruction set d on chip debug support enabling the

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Unformatted text preview: ; 5 stage pipeline • Used in ARM9TDMI 143/213 ARM9TDMI 5-stage Pipeline Organization • Fetch Institute of Electronics, National Chiao Tung University – • Decode – • An operand is shifted and the ALU result generated. If the instruction is a load or store, the memory address is computed in the ALU Buffer/Data – • The instruction is decoded and register operands read from the register file. There are 3 operand read ports in the register file so most ARM instructions can source all their operands in one cycle Execute – • The instruction is fetched from memory and placed in the instruction pipeline Data memory is accessed if required. Otherwise the ALU result is simply buffered for one cycle Write Back – The results generated by the instruction are written back to the register file, including any data loaded from memory 144/213 Data Forwarding • Institute of Electronics, National Chiao Tung University • • • Data dependency arises when an instruction needs to use the result of one of its predecessors before the result has returned to the register file => pipeline hazards Forwarding paths allow results to be passed between stages as soon as they are available 5-stage pipeline requires each of the three source operands to be forwarded from any of the intermediate result registers Still one load stall LDR rN,[…] ADD r2,r1,rN ;use rN immediately – one stall – compiler rescheduling 145/213 ARM7TDMI Processor Core Institute of Electronics, National Chiao Tung University • Current low-end ARM core for applications like digital mobile phones • TDMI – T: Thumb, 16-bit compressed instruction set – D: on-chip Debug support, enabling the processor to halt in response to a debug request – M: enhanced Multiplier, yield a full 64-bit result, high performance – I: Embedded ICE hardware • Von Neumann architecture • 3-stage pipeline, CPI ~1.9 146/213 ARM7TDMI Block Diagram Institute of Electronics, National Chiao Tung University 147/213 ARM7TDMI Core Diagram Institute of Electronics, National Chiao Tung University 148/213 ARM7TDMI Interface Signals (1/4) Institute of Electronics, National Chiao Tung University 149/213 ARM7TDMI Interface Signals (2/4) • Clock control Institute of Electronics, National Chiao Tung University – all state change within the processor are controlled by mclk, the memory clock – internal clock = mclk AND \wait – eclk clock output reflects the clock used by the core • Memory interface – 32-bit address A[31:0], bidirectional data bus D[31:0], separate data out Dout[31:0], data in Din[31:0] – \mreq indicates a processor cycle which requires a memory access – seq indicates that the memory address will be sequential to that used in the previous cycle 150/213 ARM7TDMI Interface Signals (3/4) Institute of Electronics, National Chiao Tung University – lock indicates that the processor should keep the bus to ensure the atomicity of the read and write phase of a SWAP instruction – \r/w, read or write – mas[1:0], encode memory access size - byte, half-word or word – bl[3:0], externally controlled enables on latches on each of the 4 bytes on the data input bus • MMU interface – \trans (translation control), 0:user mode, 1:privileged mode – \mode[4:0], bottom 5 bits of the CPSR (inverted) – abort, disallow access • State – T bit, whether the processor is currently executing ARM or Thumb instructions • Configuration – bigend, big-endian or li...
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