02_ARM_Processor_Core_and_Instruction_Sets

Interrupt controller icbase the base address of the

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Unformatted text preview: I_WriteC SWI_Exit ENTRY START ADR LOOP LDRB CMP SWINE BNE SWI TEXT = END HelloW,CODE,READONLY EQU &0 EQU &11 ;declare code area ;output character in r0 ;finish program ;code entry point r1,TEXT ;r1-> “Hello World” r0,[r1],#1 ;get next byte r0,#0 ;check for text end SWI_WriteC ;if not end print … LOOP ;… and loop back SWI_Exit ;end of execution “Hello World”,&0a,&0d,0 ;end of program source • The following tools are needed – – – – a text editor to type the program into an assembler to translate the program into ARM binary code an ARM system or emulator to execute the binary code a debugger to see what is happening inside the code 188/213 Program Design Institute of Electronics, National Chiao Tung University • Start with understanding the requirements, translate the requirements into an unambiguous specifications • Define a program structure, the data structure and the algorithms that are used to perform the required operations on the data • The algorithms may be expressed in pseudo-code • Individual modules should be coded, tested and documented • Nearly all programming is based on high-level languages, however it may be necessary to develop small software components in assembly language to get the best performance 189/213 System Architecture (1/2) • Institute of Electronics, National Chiao Tung University • • ARM processor, memory system, buses, and the ARM reference peripheral specification The reference peripheral specification defines a basic set of components, providing a framework within which an operating system can run but leaving full scope for application-specific system Components include – – – – • a memory map an interrupt control a counter timer a reset controller with defined boot behavior, power-on reset detection, a “wait for interrupt” pause mode The system must define – the base address of the interrupt controller (ICBase) – the base address of the counter-timer (CTBase) – the base address of the reset and pause controller (RPCBase) All the address of the registers are relative to one of the base addresses 190/213 System Architecture (2/2) • Institute of Electronics, National Chiao Tung University • • Interrupt controller provides a way of enabling, disabling (by mask) and examining the status of up to 32 level-sensitive IRQ sources and one FIQ source Two 16-bit counter-timers, controlled by registers. The counters operate from the system clock with selectable pre-scaling Reset and pause controller includes some registers – the readable registers give identification and reset status information – the writable registers can set or clear the reset status, clear the reset map and put the system into pause mode where it uses minimal power until an interrupt wakes it up again • Add application-specific peripherals 191/213 Hardware System Prototype Institute of Electronics, National Chiao Tung University • Verifying the function correctness of hardware blocks, software modules(on-developing) and speed performance is acceptable • Simulating the system using software tools => slower, can’t verify the full system • Hardware Prototyping – building a hardware platform by pre-existing or on-developing components for system verification and software development – “ARM Integrator” or “Rapid Silicon Prototyping” 192/213 ARM Integrator System Bus External Bus Interface Peripheral Input/ Output Core Module Connectors Instit...
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