02_ARM_Processor_Core_and_Instruction_Sets

R0 r2r14 save work and link regs bl sub2 99213

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Unformatted text preview: o Tung University 97/213 Conditional Execution Institute of Electronics, National Chiao Tung University • An unusual feature of the ARM instruction set is that conditional execution applies not only to branches but to all ARM instructions Bypass • CMP BEQ ADD SUB … r0,#5 Bypass r1,r1,r0 r1,r1,r2 ;if(r0!=5) ;{r1=r1+r0-r2} CMP r0,#5 ADDNE r1,r1,r0 SUBNE r1,r1,r2 Whenever the conditional sequence is 3 instructions or fewer it is better (smaller and faster) to exploit conditional execution than to use a branch if((a==b)&&(c==d)) e++; CMP r0,r1 CMPEQ r2,r3 ADDEQ r4,r4,#1 98/213 Branch and Link Instructions Institute of Electronics, National Chiao Tung University • Perform a branch, save the address following the branch in the link register, r14 SUBR BL SUBR … … MOV PC,r14 ;branch to SUBR ;return here ;subroutine entry point ;return • For nested subroutine, push r14 and some work registers required to be saved onto a stack in memory SUB1 SUB2 BL SUB1 … STMFD r13!,{r0-r2,r14} ;save work and link regs BL SUB2 … … 99/213 Subroutine Return Instructions SUB Institute of Electronics, National Chiao Tung University • … MOV PC,r14 ;copy r14 into r15 to return Where the return address has been pushed onto a stack SUB1 STMFD r13!,{r0-r2,r14} ;save work regs and link BL SUB2 … LDMFD r13!,{r0-e12,PC} ;restore work regs & return 100/213 Supervisor Calls Institute of Electronics, National Chiao Tung University • The supervisor is a program which operates at a privileged level, which means that it can do things that a user-level program cannot do directly (e.g. input or output) • SWI instruction – software interrupt or supervisor call SWI SWI_WriteC ;output r0[7:0] SWI SWI_Exit ;return to monitor program 101/213 Jump Tables Institute of Electronics, National Chiao Tung University • To call one of a set of subroutines, the choice depending on a value computed by the program BL JUMPTAB … JUMPTAB CMP r0,#0 BEQ SUB0 CMP r0,#1 BEQ SUB1 CMP r0,#2 SUBTAB BEQ SUB2 … BL JUMPTAB … JUMPTAB ADR r1,SUBTAB ;r1->SUBTAB CMP r0,#SUBMAX ;check for overrun LDRLS PC,[r1,r0,LSL#2];if OK,table jump B ERROR DCD SUB0 DCD SUB1 DCD SUB2 … • The ‘DCD’ directive instructs the assembler to reserve a word of store and to initialize it to the value of the expression to the right, which in these cases is just the address of the label. 102/213 Branch and Branch with Link (B,BL) • B{L}{<cond>} <target address> Institute of Electronics, National Chiao Tung University – <target address> is normally a label in the assembler code. 31 28 27 25 24 23 cond 1110 L 0 24-bit signed word offset 24-bit offset, sign-extended, shift left 2 places + PC (address of branch instruction + 8) target address 103/213 Examples • Unconditional jump Institute of Electronics, National Chiao Tung University LABEL • B … … LABEL Loop ten times MOV r0,#10 Loop … SUBS r0,#1 BNE Loop … • Call a subroutine SUB • BL SUB … … MOV PC,r14 Conditional subroutine call CMP r0,#5 BLLT SUB1 BLGE SUB2 ; if r0<5, call SUB1 ; else call SUB2 104/213 Branch, Branch with Link and eXchange • B{L}X{<cond>} Rm Institute of Electronics, National Chiao Tung University – the branch target is specified in a register, Rm – bit[0] of Rm is copied into the T bit in CPSR; bit[31:1] is moved into PC – if Rm[0] is 1, the processor switches to execute Thumb instructions and begins executing at the address in Rm aligned to a...
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This note was uploaded on 08/23/2009 for the course IEE 5016 taught by Professor Tian-sheuanchang during the Spring '05 term at National Chiao Tung University.

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