03_SOC_Design_flow - SOC Design Flow Challenges of SoC Era...

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Unformatted text preview: SOC Design Flow Challenges of SoC Era Institute of Electronics, National Chiao Tung University • Deign complexity – – – – – – Validation & Verification Design space exploration Integration Timing & power Testing Packaging • Time to market • The cost 1 From Requirement to Deliverables Institute of Electronics, National Chiao Tung University Hierarchy Refinemenet Hierarchy Validaton Customer Needs Product Deliver System Function System Vaildation "Pattern" System Function Architecture Architecture Verification Behavioral Behavioral RTL Logical Netlist Abstract Test Patern Layout Mask Logical Device Wafer Real Fab 2 Five SoC Design Issues Institute of Electronics, National Chiao Tung University • To manage the design complexity – – – – – Co-design IP modeling Timing closure Signal Integrity Interoperability 3 How to Conquer the Complexity Institute of Electronics, National Chiao Tung University • Use a known real entity – A pre-designed component (reuse) – A platform • Partition – Based on functionality – Hardware and software • Modeling – At different level – Consistent and accurate 4 SoC Design Flow System Level Design High Level Algorithm Model C/C++/COSSAP/VCC/MATLAB Hardware/Software Partition N2C/VCC Communication Refinement Hardware Design N2C/Port-C/VCC Front End Back End Hardware/Software Coverification N2C/Seamless/"Q/Bridge" RTOS Device Driver WinCE/VxWorks Driveway API Embedded Software Software Design Institute of Electronics, National Chiao Tung University Specification Chip 5 Physical Design Flow Institute of Electronics, National Chiao Tung University • In VDSM Specification – Interconnect dominates delay – Timing closure – Signal integrity • Traditional design flow System Level Design High Level Design Front End – Two-step process – Physical design is performed independently after logic design Synthesis P&R • New design flow – Capture real technology behaviors early in the design flow – Break the iteration between physical design and logic design Functional Verification Timing Simulation Back End LVS/DRC RC Extraction Chip 6 Making Sense of Interconnect Wire Gate Percentage of Delay Institute of Electronics, National Chiao Tung University • At 0.35u, timing convergence started to become a problem. • At 0.25u, it started to significantly impact the work of the designer. • At 0.18u, if not accounted for, it actually causes designs to fail. 1.0u Source: Avant! 0.5u 0.25u 0.18u Silicon Technology Source: Synopsys 7 Interconnect Power Consumption in DSM Institute of Electronics, National Chiao Tung University • DSM effects in energy dissipation: cross-coupling capacitances Source: Y. Zorian, S. Dey, and M. Rodgers, “Test of Future System-on-Chips,” Proceeding of the 2000 International Conference on Computer-Aided Design, 392-398 8 Signal Integrity and Timing Closure • Root causes of both Signal Integrity and Timing Closure Institute of Electronics, National Chiao Tung University – Inadequate interconnect modeling techniques – No effective design methodology • Synthesis timing does not correlate with physical timing – Factors • • • • Coupling capacitance increases Interconnect resistance increases Device noise margins decrease Higher frequencies result in on-chip inductive effects – Problems • • • • Signal electromigration Antenna effects Crosstalk delay Crosstalk noise 9 Example - Crosstalk Delay Institute of Electronics, National Chiao Tung University • Net-to-net coupling capacitance dominates as a percentage of total capacitance in VDSM. • The coupling capacitance can be multiplied by the Miller Effect – Wire capacitance can be off by 2X if the adjacent wires are switching in the opposite direction. – The coupling capacitance can be much less than expected if the wires are switching in the same direction • Both have to be considered during timing analysis to fully account for setup and hold constraints. 10 New Physical Design Flow Needed Specification Institute of Electronics, National Chiao Tung University • Bring physical information into the logical design • Overview of solutions – – – – Single pass methodology Synthesis-driven layout Layout-driven synthesis All-Integrated (optimization, analysis and layout) layout System Level Design High Level Design Front End Synthesis P&R Timing Simulaton Synthesis Back Annotated Delay Sign-off Package P&R Functional Verification Back End LVS/DRC RC Extraction Chip 11 – Complete functional simulation of the chip at close to real time – Run real software 100M 10M 1M Emulation 100K 10K 1K 100 10 Acceleration Simulation Sili con IP M Ve r ode ific atio ls nS erv ices Institute of Electronics, National Chiao Tung University • Emulation in “virtual silicon” CPS (Cycle/Second HW/SW Cosimulation Through Emulation Source: IKOS Systems Inc • Tools to enable simulation between EDAs and emulators – – – – Cycle-based simulators Full-timing simulators Instruction set simulators E.g. Quickturn Q/Bridge • Expensive, long learning curve and set-up time 12 Embedded Software Architecture for SoC Design Institute of Electronics, National Chiao Tung University MMI/GUI Host Application Error Handling Memory Allocation Diagnostics Message Manager Task controller State Machine Application Program Interface Display Services Stack Protocol File Manager Alarm Services Event Manager Library Data I/O Kernel Services Device Drivers Hardware 13 Software Development Institute of Electronics, National Chiao Tung University • Porting software to a new processor and RTOS – Using a common RTOS abstraction layer • The evolution of embedded system in the future – An standard RTOS Application Software Application Software Optimized API New API Needed RTOS New RTOS Microprocessor New Microprocessor Old New 14 Software Performance Estimation Institute of Electronics, National Chiao Tung University • Have to take the following into account – – – – Instruction set Bus loading Memory fetching Register allocation • Example: Cadence VCC technology – – – – CPU characterized as Virtual Processor Model Using a Virtual Machine Instruction Set SW estimation using annotation into C-Code Good for early system scheduling, processor load estimation • Two orders of magnitude faster than ISS • Greater than 80% accuracy 15 Tester Partitioning Institute of Electronics, National Chiao Tung University High bandwidth Source/ Sink Logic Source/ Sink Memory Source/ Sink External Tester Embedded Tester Source/ Sink External Tester Logic Source/ Sink Memory Source/ Sink PLL Low bandwidth Source/ Sink PLL Embedded Tester Source: Y. Zorian, S. Dey, and M. Rodgers, “Test of Future System-on-Chips,” Proceeding of the 2000 International Conference on Computer-Aided Design, 392-398 16 Self-Testing of Embedded Processor Cores Institute of Electronics, National Chiao Tung University • Logic BIST – Based on the application of pseudo random test patterns generated by on-chip test pattern generators like LFSRs. – Cannot always achieve very high fault coverage for processor cores. • Instruction-based self-test techniques – Rely on generating and applying random instruction sequences to processor cores. – The approach determines the structural test needs of processor components – Advantage: programmability and flexibility 17 Platform-based Design Block Authoring Functional Design Executable Specification System Analysis Chip Specification/ IP Selection Static Verification Implementation RTOS/ Application Selection Integration Planning Static Verification IP Portfolio Physical Verification Authoring Guide Module Development Chip Implementation Physical Verification Cell Libraries System Analysis Dynamic Verification Testbenches Block Design Planning Formal IP Handoff Testbenches Virtual System Analysis Block Specification Dynamic Verification Architecture Design Integration Design SW Development Chip Integration Digital & Mixed Signal Physical Design Institute of Electronics, National Chiao Tung University Supporting Manufacturing Link Technology VC Delivery Integration IP Portfolio Platform SW Development Links SW Distribution RTOS/ Applications Source: “Surviving the SOC Revolution - A Guide to Platform-Based Design” by Henry Chang et al, Kluwer Academic Publishers, 1999 18 Design Entry Institute of Electronics, National Chiao Tung University Gate level Truth table FSM Waveform 1K~10K Manage Size and Run-Time RTL level 10K~100k System level modeling 100K~100M 19 Hardware Platform-Based Design Institute of Electronics, National Chiao Tung University It is a “meet-in-the-middle” approach. System Integrator Perspective Platform Provider Perspective 20 System-Level Design Institute of Electronics, National Chiao Tung University • Goal – To define the platform that satisfies the system functions with performance/cost tradeoff • Platform design – Bus structure – IP and their function design Customized instructions Parallelism Command parameters Configurable parameters IP parameters – Control scheme – Data communication (bandwidth) 21 Control Scheme Model Institute of Electronics, National Chiao Tung University Interrupts Interrupt Status Polling (timer) Status Command Configuration Data Receive Buffer Data Transmit Buffer 22 Some Helps in System-Level Design Institute of Electronics, National Chiao Tung University • Cadence VCC (Virtual Component Codesign, from Cadence Berkely Labs) – Performance simulation – Communication refinement technology • Vast Systems Technology – VPM (Virtual Processor Model) – HW/SW codesign • CoWare N2C (Napkin-to-chip) – Interface synthesis • SystemC 23 Cadence’s VCC VCC Platform Function VCC Platform Architecture SPW Floating Point Algorithm Analysis VCC Performance Analysis and Platform Configuration SPW Fixed Point Algorithm Analysis Software Development VCC Functional System Integration Hardware Development SPW DSP Behavioral Specification SPW HDS Block Implementation VCC Communication Synthesis Communication Integration VCC Hardware Assembly VCC Software Assembly IP Block System Integration Block Level Specification IP Block Authoring Institute of Electronics, National Chiao Tung University Full System Specification HW/SW Verifier - Verification Cockpit - NC-SIM RTL Block Verification and HW-SW-Co-Verification Synthesis / Place & Route etc. 24 An Opportunity To Do It Right ! Institute of Electronics, National Chiao Tung University 25 SystemC Heritage Institute of Electronics, National Chiao Tung University 26 SystemC Roadmap Institute of Electronics, National Chiao Tung University 27 The Intent of Different Level of Model Institute of Electronics, National Chiao Tung University • Design exploration at higher level – – – – Import of top-level constraint and block architecture Hierarchical, complete system refinement Less time for validating system requirement More design space of algorithm and system architecture • Simple and efficient verification and simulation – – – – Functional verification Timing simulation/verification Separate internal and external (interface) verification Analysis: power and timing • Verification support 28 SystemC Institute of Electronics, National Chiao Tung University • SystemC is a modeling platform – – – – C++ extensions to add hardware modeling constructs a set C++ class library simulation kernel supports different levels of abstraction Good Candidate for Task Level Mapping 29 Level of abstraction in SystemC Institute of Electronics, National Chiao Tung University 30 SystemC Design Flow Institute of Electronics, National Chiao Tung University 31 Example Institute of Electronics, National Chiao Tung University Source: SystemC Users Forum, DAC, June 2000 32 Implementing Virtual Prototypes Institute of Electronics, National Chiao Tung University Functionality partition • Module specification • Communication refinement Func_A() { ...... IQ(); Func_B() { ...... ...... } IDCT(); ...... } MC IQ_IDCT() { ...... IQ(); IDCT(); ...... } MC FIFO IQIDCT IQIDCT 33 Functionality Partition Institute of Electronics, National Chiao Tung University • Separating communication and computation • Using hierarchy to group related functionality • Choosing the granularity of the basic parts 34 Module Specification (1/2) Process A Institute of Electronics, National Chiao Tung University entry() { ...... Z = func_B(X,Y); ...... } 2 func_B(X,Y) { Z = X+Y; retuen Z; } 1 Process B entry() { ...... X.write(); Y.write(); Z.read(); ...... } X Y Z Process C entry() { X.read(); Y.read(); Z = X+Y; Z.write(); } 3 1. Pull out functionality into new created process 2. Replace function call with inter-process communcation. 3. Instantiate new process and define channels to connect them. 35 Module Specification (2/2) Institute of Electronics, National Chiao Tung University • Abstraction Levels – Untimed Functional Level – Processes execute in zero time but in order – Timed Functional Level – Bus-Cycle Accurate Level • Transaction on bus are modeled cycle accurate • Cycle Accurate Level – Behavior is clock cycle accurate 36 Communication Refinement Institute of Electronics, National Chiao Tung University Key Guarantee consistency of communication during refinement 37 Software Performance Estimation Institute of Electronics, National Chiao Tung University • Have to take the following into account – – – – Instruction set Bus loading Memory fetching Register allocation • Example: Cadence VCC technology – – – – CPU characterized as Virtual Processor Model Using a Virtual Machine Instruction Set SW estimation using annotation into C-Code Good for early system scheduling, processor load estimation • Two orders of magnitude faster than ISS • Greater than 80% accuracy 38 Discussion: Commonality and Differentia Institute of Electronics, National Chiao Tung University • Differentiae – Processor core (e.g., customized inst. set) – IP parameterized – IP add/move • Design methodology of platform – System-level – Platform-level design methodology • Design flow • Models • Tools (EDA venders, 3rd party or home-made) 39 Summary Institute of Electronics, National Chiao Tung University • Platform-based design – From board design to SoC design – From executable spec., i.e., C/C++, to SystemC • Modeling – Performance evaluation – Task mapping – Communication refinement 40 ...
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This note was uploaded on 08/23/2009 for the course IEE 5016 taught by Professor Tian-sheuanchang during the Spring '05 term at National Chiao Tung University.

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