03_VCI_and _AMBA - VCI Interface and AMBA Bus Outline...

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Unformatted text preview: VCI Interface and AMBA Bus Outline Institute of Electronics, National Chiao Tung University • VCI Interface Standards • AMBA - On Chip Buses • AMBA 3.0 - AXI 1/142 Outline Institute of Electronics, National Chiao Tung University • VCI Interface Standards • AMBA - On Chip Buses • AMBA 3.0 - AXI 2/142 Virtual Component Interface - VCI Institute of Electronics, National Chiao Tung University • What is VCI – A request-response protocol, contents and coding, for the transfer of requests and responses • Why VCI – Other IP blocks not available ‘wrapped’ to the on-chip communications may work with IP wrappers. VCI is the best choice to start with for an adaptation layer • VCI specifies – Thee levels of protocol, compatible each other • Advanced VCI (AVCI), • Basic VCI (BVCI) • Peripheral VCI (PVCI) – Transaction language 3/142 VCI Point-to-Point Usage Institute of Electronics, National Chiao Tung University • Simplicity: small footprint and high bandwidth – Initiator only request – Target only respond – If a VC needs both, implement parallel initiator and target interfaces • Star topology Request Initiator Target Response Point-to-point usage 4/142 VCI Usage with a Bus Institute of Electronics, National Chiao Tung University • Used as the interface to a wrapper (a connection to a bus) – OCB suppliers provide VCI wrappers. – EDA vendors provide tools to create wrapper automatically Initiator VC Target VC VCI Initiator VCI Target VCI Point to Point VCI Target VCI Initiator Initiator Wrapper Target Wrapper Bus Master Bus Slave Any Bus VCI usage with a bus 5/142 Split Protocol Institute of Electronics, National Chiao Tung University • The timing of the request and the response are fully separate. The initiator can issue as many requests as needed, without waiting for the response. BVCI AVCI PVCI order kept request tagged with identifiers, allow different order no split protocol each request must be followed by a response before the initiator can issue a new request 6/142 Initiator – Target Connection (PVCI) Institute of Electronics, National Chiao Tung University • The request contents and the response contents are transferred under control of the protocol: 2wire handshake Valid (VAL) and Acknowledge (ACK) 7/142 Control Handshake • Synchronous Institute of Electronics, National Chiao Tung University • Asynchronous 8/142 Request and Response Contents Institute of Electronics, National Chiao Tung University • Main PVCI features CLOCK RESETN System Signals VAL EOP Handshake ACK Initiator Target ADDRESS[n-1:0] BE[b-1:0 | 0:b-1] Contents WDATA[8b-1:0] RERROR[E:0] RDATA[8b-1:0] – – – – – Up to 32-bit Address Up to 32-bit Read Data Up to 32-bit Write Data Synchronous Allows for 8-bit, 16-bit, and 32-bit devices – 8-bit, 16-bit, and 32-bit Transfers – Simple packet, or ‘burst’ transfer 9/142 PVCI Protocol Institute of Electronics, National Chiao Tung University • Transfer Request – Read8, Read16, Read32, Read N cells – Write8, Write16, Write32, Write N cells • Transfer Response – Not Ready – Transfer Acknowledged – Error • Packet Transfer – The packet (burst) transfer makes is to transfer a block of cells with consecutive addresses – While the EOP signal is de-asserted during a request, the address of the next request will be ADDRESS+cell_size 10/142 Initiator – Target Connection (BVCI) Institute of Electronics, National Chiao Tung University • The request and response handshakes are independent of each other – Request handshake: CMDVAL and CMDACK – Response handshake: RSPVAL and RSPACK 11/142 Cells, Packets, and Packet Chains Institute of Electronics, National Chiao Tung University • Each handshake transfers a cell across the interface. The cell size is the width of the data passing across a VCI. – 1, 2, 4, 8, or 16 bytes for BVCI – 1, 2, 4, bytes for PVCI • Cell transfers can be combined into packets, which may map onto a burst on a bus. – A VCI operation consists of a request packet and a response packet – Packets are atomic – Packets are similar in concept to “frames” in PCI • Packets can be combined into chains, to allow longer chains of operations to go uninterrupted. 12/142 Request and Response Contents Institute of Electronics, National Chiao Tung University • Request contents are partitioned into three signal groups and validated by the CMDVAL signal – Opcode, specify the nature of the request (read or write) – Packet Length and Chaining – Address and Data • Response contents validated with the RSPVAL. Each request has its response. – Response Error – Read Data 13/142 BVCI Signals CLOCK RESETN Institute of Electronics, National Chiao Tung University System Signals CMDVAL CMDACK Request Handshake ADDRESS[n-1:0] BE[b-1:0 | 0:b-1] CFIXED CLEN[q-1;0] Initiator Request Contents CMD[1:0] CONTIG Target WDATA[8b-1:0] EOP CONST PLEN[k-1:0] WRAP RSPACK Response Handshake RSPVAL RERROR[E:0] Response Contents REOP RDATA[8b-1:0] 14/142 BVCI Protocol Institute of Electronics, National Chiao Tung University • The protocol has three stacked layers: transaction layer, packet layer, and cell layer • Transaction layer: A pair of request and response transfers – Above hardware implementation – A series of communicating objects that can be either hardware or software modules – The information exchanged between initiator and target nodes is in the form of a request-response pair 15/142 Packet Layer Institute of Electronics, National Chiao Tung University • The packet layer adds generic hardware constraints to the system model • In this layer, VCI is a bus-independent interface, just physically point-to-point • A transaction is called a “VCI operation” if the information is exchanged using atomic request and response transfers. In a packet layer, a VCI transaction decomposes into one or more operations. 16/142 Packet Institute of Electronics, National Chiao Tung University • Packet is the basic unit of information that can be exchanged over the VCI in an atomic manner. • Multiple packets can be combined to form larger, non-atomic transfer units called packet chains. • A VCI operation is a single request-response packet pair. • Packet length is the number of bytes transferred • The content of a packet depends on whether it is a request or response packet and the type of operation being carried out - such as read, write, etc. 17/142 Cell Layer Institute of Electronics, National Chiao Tung University • The cell layer adds more hardware details such as interface width, handshake scheme, wiring constraints, and a clock to the system. • A cell is the basic unit of information, transferred on rising CLOCK edges under the VAL-ACK handshake protocol, defined by the cell layer. Multiple cells constitute a packet. • Both request and response packets are transferred as series of cells on the VCI. The number of cells in a packet depends on the packet length and the interface width. 18/142 BVCI Operations Institute of Electronics, National Chiao Tung University • The basic transfer mechanism in VCI is packet transfer. A packet is sent as a series of cells with the EOP field in the last cell set to value 1. Each cell is individually handshaken under the VAL-ACK handshake. Either the initiator or the target can insert wait cycles between cell transfers by de-asserting VAL or ACK. • Transfer Requests – Read/Write a cell – Read/Write a packet from random/contiguous addresses – Read/Write a packet from one address – Issue a chain of packets • Transfer Responses – Read/Write cell/packet successful – Read/Write packet general error – Read/Write bad data error – Read/Write Abort disconnect 19/142 Advanced VCI Institute of Electronics, National Chiao Tung University • AVCI supports out-of-order transactions and an advanced packet model • Advanced Packet Model – Request and response packets do not have the same size – Need • request packet: one cell, set the start address and address behavior • response packet: many cells, read data return • Arbitration hiding – pipelines of both the request and response packets • Source Identification – a unique identifier for each initiator 20/142 AVCI Protocol Institute of Electronics, National Chiao Tung University • Still 3 layers similar to BVCI. No difference in the transaction layer, slightly differ in the packet and cell layers • Packet layer • Cell layer – AVCI cell layer differs from BVCI with some additional fields, with side band signals for arbitration hiding – Arbitration hiding signals are separately handshaken 21/142 Outline Institute of Electronics, National Chiao Tung University • VCI Interface Standards • AMBA - On Chip Buses • AMBA 3.0 - AXI 22/142 ARM OCB - AMBA Institute of Electronics, National Chiao Tung University • Advanced Microcontroller Bus Architecture (AMBA) • AMBA 2.0 specifies – – – – the Advanced High-performance Bus (AHB) the Advanced System Bus (ASB) the Advanced Peripheral Bus (APB) test methodology ARM Core EBI/TIC On-Chip RAM AHB/ASB DMA Master UART PIO APB Bridge Timer Keypad A typical AMBA system 23/142 Features of AMBA Institute of Electronics, National Chiao Tung University • AHB is superior to ASB in – performance and synthesizibility and timing verification Advanced High-performance Bus (AHB) High performance Pipelined operation Multiple bus master Burst transfers A single centralized decoder Advanced System Bus (ASB) High performance Pipelined operation Multiple bus master Burst transfers A single centralized decoder Advanced Peripheral Bus (APB) Low power Simple interface APB access MUST take 2 PLCK cycles Split transactions single-cycle bus master handover single-clock edge operation non-tristate implementation wider data bus configurations (8/16/32/64/128 bits) 24/142 Notes on the AMBA Specification Institute of Electronics, National Chiao Tung University • Technology independence – The specification only details the bus protocol at the clock cycle level • Electrical characteristics – No information regarding the electrical characteristics is supplied • Timing specification – The system integrator is given maximum flexibility in allocating the signal timing budget amongst the various modules on the bus – More free, but may also be more danger and timeconsuming 25/142 Notes on AMBA (1/3) Institute of Electronics, National Chiao Tung University • Split transaction – NOT truly split transaction - the arbiter only masks the access of the master which gets a SPLIT transfer response – Master does not need extra slave interface – Only allows a single outstanding transaction per bus master • NOT support Sideband signals – Sideband signals: reset, interrupts, control/status, generic flags, JTAG test interface, etc. – Require the system integrator to deal with them in an ad-hoc way for each system design. – Good references of sideband signals: VSIA VCI or Sonics OCP OCP: Open Core Protocol 26/142 Notes on AMBA (2/3) Institute of Electronics, National Chiao Tung University • DMA channels – Use AHB protocol • E.g. PrimeCell SDRAM Controller • Easy to connect to another AHB bus – Adopt user defined protocol • Lower the complexity of the DMA interface 27/142 Notes on AMBA (3/3) Institute of Electronics, National Chiao Tung University • APB does not support WAIT transaction – Access status register first, then access data register – Alternative: designed as AHB slaves – Multiple AHB/APB to reduce loading Wipro’s SOC-RaPtorTM Architecture 28/142 AHB Interconnect Institute of Electronics, National Chiao Tung University • Bus master drives the address and control • Arbiter selects one of the master 29/142 AHB Operation (1/2) Institute of Electronics, National Chiao Tung University • Master asserts a request signal to the arbiter. Arbiter then gives the grant to the master. • A granted bus master starts an AHB transfer by driving WRAP4 address and control signals: 0x10 – – – – address direction width burst forms • Incrementing burst: not wrap at address boundaries • Wrapping burst: wrap at particular address boundaries • Write data bus: move data from the master to a slave • Read data bus: move data from a slave to the master 0x14 0x18 0x1C 0x20 0x24 INCR4 Address wrap in 4word boundary 30/142 AHB Operation (2/2) Institute of Electronics, National Chiao Tung University • All slaves sample the address Data can be extended using the HREADY signal, when LOW, wait states be inserted and allow extra time for the slave to provide or sample data • During a transfer the slave shows the status using the response signals HRESP[1:0] – OKAY: transfer progressing normally when HREADY is HIGH, transfer has completed successfully – ERROR: transfer error – RETRY and SPLIT: transfer can’t complete immediately, but the bus master should continue to attempt the transfer • As burst transfer, the arbiter may break up a burst and in such cases the master must re-request for the bus. 31/142 Address Decoding Institute of Electronics, National Chiao Tung University • A central address decoder provides HSELx for each slave • Minimum address space that can be allocated to a single slave is 1K Byte – No incrementing transfers can over a 1K Byte boundary 32/142 AHB Master Institute of Electronics, National Chiao Tung University • Initiate read and write by providing an address and control interface • Processor, DMA, DSP test interface 33/142 AHB Slave Institute of Electronics, National Chiao Tung University • Respond to a read or write operation within a given address-space range • Back to the master the success, failure or waiting HPROT[3:0] HREADY_in 34/142 Basic Transfer Institute of Electronics, National Chiao Tung University Master action Slave action Drive action Sample action Address & Control A Data & Response B C D A B C D • Address phase : one cycle Data phase : one or several cycles • 1st clock : master drives address and control • 2nd clock : slave samples address and control • 3rd clock : bus master sample the slave’s response 35/142 Multiple Transfers • Three transfers to run related address A, B, and C Institute of Electronics, National Chiao Tung University Address & control Data & Response A B A 1 wait cycle for address B C B C 36/142 Transfer Type (1/2) Institute of Electronics, National Chiao Tung University HTRANS[1:0] 00 Type IDLE Descripton 01 BUSY Masters cannot take next trnsfer place immediately during a burst transfer. Slaves take actions as they take for IDLE. 10 NONSEQ Indicates the first transfer of a burst or a single transfer 11 SEQ Slaves must always provide a zero wait state OKAY response to IDLE transfers and the transfer should be ignored by the slave The remaining transfers in a burst are SEQUENTIAL. The control information is identical to the previous transfer. 37/142 Transfer Type (2/2) Institute of Electronics, National Chiao Tung University • • During T2-T3, master is unable to perform the second transfer of burst immediately and therefore the master uses BUSY transfer to delay the start of the next transfer. During T5-T6, slave is unable to complete access immediately, and uses HREADY to insert a single wait state. 38/142 Burst Operation Institute of Electronics, National Chiao Tung University • 4-, 8-, 16-beat • e.g., 4-beat, start address 0x34, wrapping burst four transfers: 0x34, 0x38, 0x3C, 0x30 • Burst length HBURST[1:0] Type Descripton 000 SINGLE Single Transfer 001 INCR Incrementing burst of unspecified length 010 011 WRAP4 INCR4 4-beat wrapping burst 4-beat incrementing burst 100 WRAP8 INCR8 WRAP16 INCR16 0x38 0x3C 16-beat wrapping burst 111 0x34 8-beat incrementing burst 110 0x30 8-beat wrapping burst 101 WRAP4 16-beat incrementing burst 0x40 0x44 • Limitation: bursts must not cross a 1k Byte address boundary 39/142 Four-beat Wrapping Burst Institute of Electronics, National Chiao Tung University 40/142 Control Signals Institute of Electronics, National Chiao Tung University • Have exactly the same timing as the address bus • Must remain constant throughout a burst of transfers • Types – HWRITE – HSIZE[2:0] – HPROT[3:0]) : Transfer direction : Transfer size : Protection control indicate if the transfer is: • An opcode fetch or data access • A privileged mode access or user mode access • Access is cacheable or bufferable (for bus masters with a memory management unit) 41/142 Transfer Responses (from slave) Institute of Electronics, National Chiao Tung University HPROT[3:0] HREADY_in 42/142 Transfer Responses Institute of Electronics, National Chiao Tung University • HREADY • HRESP[1:0] 00 01 10 11 Response OKAY ERROR RETRY SPLIT • Two-cycle response – ERROR & RETRY & SPLIT – To complete current transfer, master can take following action Cancel for RETRY Cancel for SPLIT Either cancel or continue for ERROR 43/142 Examples of Two-cycle Response • Retry response Institute of Electronics, National Chiao Tung University Cancel • Error response Wait Error Error 44/142 Data Buses Institute of Electronics, National Chiao Tung University • HWDAA : 32 bits • RDATA : 32 bits • Endianness : fixed, lower power; higher performance 45/142 Narrow Slave on A Wide Bus Institute of Electronics, National Chiao Tung University 46/142 Wide Slave on A Narrow Bus Institute of Electronics, National Chiao Tung University 47/142 Arbitration Institute of Electronics, National Chiao Tung University 48/142 Granting Bus Access With No Wait States Institute of Electronics, National Chiao Tung University 49/142 Granting Bus Access Institute of Electronics, National Chiao Tung University Last Transfer of last bus owner Wait Wait 50/142 Bus Master Grant Signals Institute of Electronics, National Chiao Tung University Arbiter 51/142 Split Transfer HREADY_in Institute of Electronics, National Chiao Tung University HPROT[3:0] 52/142 Split Transfer Institute of Electronics, National Chiao Tung University 53/142 AHB-Lite • Requirement Institute of Electronics, National Chiao Tung University – Only one master – Slave must not issue Split or Retry response • Subset of AHB Functionality – Master: no arbitration or Split/Retry handling – Slave: no Split or Retry responses • Standard AHB masters can be used with AHB-Lite • Advantage – Master does not have to support: the following cases: • Losing bus ownership • Early bus termination • Split and Retry response – No arbiter – No Master-to-slave mux – Allows easier module design/debug 54/142 AHB-Lite Interchangeability Institute of Electronics, National Chiao Tung University 55/142 AHB-Lite Master Institute of Electronics, National Chiao Tung University 56/142 AHB-Lite Slave HREADY_in Institute of Electronics, National Chiao Tung University HPROT[3:0] 57/142 Multi-layer AHB (1/2) Institute of Electronics, National Chiao Tung University Master #1 Interconnect Matrix Slave #1 Slave #2 Master #2 Slave #3 Master #3 Slave #4 58/142 Multi-layer AHB (2/2) Institute of Electronics, National Chiao Tung University • • • Local slaves Multiple slaves on one slave port Multiple masters on one layer Mixed implementation of AHB and AHB-Lite in a multi-layer system. 59/142 Comparison among AMBA and other OCBs OPB Institute of Electronics, National Chiao Tung University Width (bits) PLB APB ASB Mbus PalmBus FISPbus 8, 16, 32 8, 16, 32,64 8, 16, 32,64 8, 16, 32 1 Data Tranfer 1 Data Tranfer Data Bus Width Data Bus Width Symbolic Symbolic Symbolic early, term term term middle. late early, middle. late AHB 8, 16, 32 32 2.9 GB/s, up to 32 8, 16, 32 2n, 183 MHz bit n=3~10 128 bit Peak Bandwidth (size/per cycle) 1 Data Tranfer Timing Guidelines % 2 Data Tranfer Synchronous Data Bus Distribu Multiple Implementation ted And- xor Or/ Multiple xor 4 bytes 0.5 bus width % 4 bytes 1 bus width rising clock edge falling clock edge* PIbus Plbus2 1 bus width rising clock edge rising clock edge Multiple Tristate xor 0.5/1 Data Tranfer (v1/v2 ) rising clock edge Tristate Source - Black : OCB 1 1.0 - Other colors : Update 60/142 ARM Cores and Their Bus Interfaces Institute of Electronics, National Chiao Tung University ARM ARM7TDMI ARM8 ARM9 ARM1020E Transistors 74,209 124,554 111,000 7,000,000 Process Technology 0.35u 0.5u 0.25u 0.18u Clock Rate 66MHz 72MHz 200MHz 400MHz Vdd 3.3V - 2.5V 1.5 MIPS 60 - 220 500 Data Bus 32bits 32bits 32-bit A 64bit W 64-bit R External memory bus interface is AMBA AHB compliant 32bits ARM System-on-Chip Architecture, by Steve Furber, Addison-Wesley, 2000 61/142 Outline Institute of Electronics, National Chiao Tung University • VCI Interface Standards • AMBA - On Chip Buses • AMBA 3.0 - AXI 62/142 Design Trends Institute of Electronics, National Chiao Tung University Source: November 2003 Issue, Nikkei Electronics Asia 63/142 Evolution of On-chip Bus Institute of Electronics, National Chiao Tung University Source: November 2003 Issue, Nikkei Electronics Asia 64/142 Problems of Existing OCBs Institute of Electronics, National Chiao Tung University Source: November 2003 Issue, Nikkei Electronics Asia 65/142 New Generations of OCBs Institute of Electronics, National Chiao Tung University Source: November 2003 Issue, Nikkei Electronics Asia 66/142 AHB/AXI Timing Institute of Electronics, National Chiao Tung University Source: November 2003 Issue, Nikkei Electronics Asia 67/142 Introduction to AXI Institute of Electronics, National Chiao Tung University • Brief history of AMBA NEC Electronics (Europe) OKI Electric Industry Philips Semiconductors AHB QUALCOMM Cadence Mentor Graphics Samsung Conexant Systems Matsushita STMicroelectronics Micronas Synopsys Epson Motorola Toshiba Corporation Ericsson Mobile Platforms AXI LSI Logic CoWare Inc. AMBA 3.0 Infineon Atmel – Over 30 participants Hewlett-Packard Company ARM • AMBA 3.0 development Fujitsu Agilent – ASB in 1995 – AHB in 1999 – AXI in 2003 Agere Systems NEC Electronics Corporation Verisity APB Source: First details of AXI, ARM 68/142 Channel Architecture Institute of Electronics, National Chiao Tung University • Four groups of signals – – – – Address Read Write Write Response ADDRESS READ DATA “A” signal name prefix “R” signal name prefix “W” signal name prefix “B” signal name prefix WRITE DATA RESPONSE Source: First details of AXI, ARM 69/142 To read ... Institute of Electronics, National Chiao Tung University 1. Master issues address ADDRESS WRITE DATA 2. Slave returns data READ DATA RESPONSE Source: First details of AXI, ARM 70/142 To write ... Institute of Electronics, National Chiao Tung University 1. Master issues address ADDRESS 2. Master gives data WRITE DATA 3. Slave acknowledges READ DATA RESPONSE Source: First details of AXI, ARM 71/142 Channels - One way flow Institute of Electronics, National Chiao Tung University AVALID ADDR AWRITE ALEN ASIZE ABURST ALOCK ACACHE APROT AID AREADY WVALID WLAST WDATA WSTRB WID WREADY RVALID RLAST RDATA RRESP RID RREADY BVALID BRESP BID BREADY • Each channel has information flowing in one direction only • READY is the only return signal Source: First details of AXI, ARM 72/142 Register slices for max frequency Institute of Electronics, National Chiao Tung University • Register slices can be applied across WID WDATA any channel WSTRB WLAST • Allows maximum WVALID frequency of operation WREADY by matching channel latency to channel delay • Allows system topology to be matched to performance requirements Source: First details of AXI, ARM 73/142 Example Register Slices A Institute of Electronics, National Chiao Tung University R A Master #1 R Isolate address timing A R A Master #2 Slave #1 Slave #2 A R R Slave #3 A Isolate poor read data setup Break long interconnect path R Slave #4 Source: First details of AXI, ARM 74/142 AMBA 2.0 AHB Burst Institute of Electronics, National Chiao Tung University ADDRESS A11 DATA A12 A13 A14 A21 A22 A23 D31 D11 D12 D13 D14 D21 D22 D23 D31 • AHB Burst – Address and Data are locked together – Single pipeline stage – HREADY controls intervals of address and data Source: First details of AXI, ARM 75/142 AXI - One Address for Burst Institute of Electronics, National Chiao Tung University ADDRESS A11 DATA A21 D11 D12 D13 D14 D31 D21 D22 D23 D31 • AXI Burst – One Address for entire burst Source: First details of AXI, ARM 76/142 AXI - Outstanding Transactions Institute of Electronics, National Chiao Tung University ADDRESS A11 DATA A21 D31 D11 D12 D13 D14 D21 D22 D23 D31 • AXI Burst – One Address for entire burst – Allows multiple outstanding addresses Source: First details of AXI, ARM 77/142 Out of Order Interface Institute of Electronics, National Chiao Tung University • Each transaction has an ID attached – Channels have ID signals - AID, RID, etc. • Transactions with the same ID must be ordered • Requires bus-level monitoring to ensure correct ordering on each ID – Masters can issue multiple ordered addresses Source: First details of AXI, ARM 78/142 AMBA 2.0 AHB Burst - Slow slave Institute of Electronics, National Chiao Tung University ADDRESS A11 A12 A13 A14 A21 A22 A23 DATA D31 D11 D12 • With AHB – If one slave is very slow, all data is held up. Source: First details of AXI, ARM 79/142 AXI - Out of Order Completion Institute of Electronics, National Chiao Tung University ADDRESS DATA A11 A21 D31 D21 D22 D23 D31 D11 D12 D13 D14 – Out of order completion allowed – Fast slaves may return data ahead of slow slaves – Complex slaves may return data out of order Source: First details of AXI, ARM 80/142 AXI - Data Interleaving Institute of Electronics, National Chiao Tung University ADDRESS DATA A11 A21 D31 D21 D22 D11 D23 D12 D31 D13 D14 – Returned data can even be interleaved – Gives maximum use of data bus – Note - Data within a burst is always in order Source: First details of AXI, ARM 81/142 AXI Multi-layer Institute of Electronics, National Chiao Tung University • Parallel paths between masters and slaves • Key Advantages – Increased bandwidth – Design flexibility • Uses the same interface protocol Master Master #1 #1 Master Master #2 #2 Bus Bus Matrix Matrix Slave Slave #1 #1 Slave Slave #2 #2 Slave Slave #3 #3 Master Master #3 #3 Slave Slave #4 #4 Source: First details of AXI, ARM 82/142 Summary Institute of Electronics, National Chiao Tung University • AXI is the next generation AMBA bus – – – – – Channel architecture Registers Slices Burst addressing Multiple outstanding bursts Out of order completion • Interconnect Options – Shared bus, multi-layer and mixed 83/142 ...
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This note was uploaded on 08/23/2009 for the course IEE 5016 taught by Professor Tian-sheuanchang during the Spring '05 term at National Chiao Tung University.

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