35u 05u 025u 018u clock rate 66mhz 72mhz 200mhz

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Unformatted text preview: lock edge rising clock edge Multiple Tristate xor 0.5/1 Data Tranfer (v1/v2 ) rising clock edge Tristate Source - Black : OCB 1 1.0 - Other colors : Update 60/142 ARM Cores and Their Bus Interfaces Institute of Electronics, National Chiao Tung University ARM ARM7TDMI ARM8 ARM9 ARM1020E Transistors 74,209 124,554 111,000 7,000,000 Process Technology 0.35u 0.5u 0.25u 0.18u Clock Rate 66MHz 72MHz 200MHz 400MHz Vdd 3.3V - 2.5V 1.5 MIPS 60 - 220 500 Data Bus 32bits 32bits 32-bit A 64bit W 64-bit R External memory bus interface is AMBA AHB compliant 32bits ARM System-on-Chip Architecture, by Steve Furber, Addison-Wesley, 2000 61/142 Outline Institute of Electronics, National Chiao Tung University • VCI Interface Standards • AMBA - On Chip Buses • AMBA 3.0 - AXI 62/142 Design Trends Institute of Electronics, National Chiao Tung University Source: November 2003 Issue, Nikkei Electronics Asia 63/142 Evolution of On-chip Bus Institute of Electronics, National Chiao Tung University Source: November 2003 Issue, Nikkei Electronics Asia 64/142 Problems of Existing OCBs Institute of Electronics, National Chiao Tung University Source: November 2003 Issue, Nikkei Electronics Asia 65/142 New Generations of OCBs Institute of Electronics, National Chiao Tung University Source: November 2003 Issue, Nikkei Electronics Asia 66/142 AHB/AXI Timing Institute of Electronics, National Chiao Tung University Source: November 2003 Issue, Nikkei Electronics Asia 67/142 Introduction to AXI Institute of Electronics, National Chiao Tung University • Brief history of AMBA NEC Electronics (Europe) OKI Electric Industry Philips Semiconductors AHB QUALCOMM Cadence Mentor Graphics Samsung Conexant Systems Matsushita STMicroelectronics Micronas Synopsys Epson Motorola Toshiba Corporation Ericsson Mobile Platforms AXI LSI Logic CoWare Inc. AMBA 3.0 Infineon Atmel – Over 30 participants Hewlett-Packard Company ARM • AMBA 3.0 development Fujitsu Agilent – ASB in 1995 – AHB in 1999 – AXI in 2003 Agere Systems NEC Electronics Corporation Verisity APB Source: First details of AXI, ARM 68/142 Channel Architecture Institute of Electronics, National Chiao Tung University • Four groups of signals – – – – Address Read Write Write Response ADDRESS READ DATA “A” signal name prefix “R” signal name prefix “W” signal name prefix “B” signal name prefix WRITE DATA RESPONSE Source: First details of AXI, ARM 69/142 To read ... Institute of Electronics, National Chiao Tung University 1. Master issues address ADDRESS WRITE DATA 2. Slave returns data READ DATA RESPONSE Source: First details of AXI, ARM 70/142 To write ... Institute of Electronics, National Chiao Tung University 1. Master issues address ADDRESS 2. Master gives data WRITE DATA 3. Slave acknowledges READ DATA RESPONSE Source: First details of AXI, ARM 71/142 Channels - One way flow Institute of Electronics, National Chiao Tung University AVALID ADDR AWRITE ALEN ASIZE ABURST ALOCK ACACHE APROT AID AREADY WVALID WLAST WDATA WSTRB WID WREADY RVALID RLAST RDATA RRESP RID RREADY BVALID BRESP BID BREADY • Each channel has information flowing in one direction only • READY is the only return signal Source: First details of AXI, ARM 72/142 Register slices for max frequency Institute of Electronics, National Chiao Tung University • Register slices can be applied across WID WDATA any channel WSTRB WLAST • Allows maximum WVALID frequency of operation WREADY by matching channel latency to chan...
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This note was uploaded on 08/23/2009 for the course IEE 5016 taught by Professor Tian-sheuanchang during the Spring '05 term at National Chiao Tung University.

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