A cell is the basic unit of information transferred

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Unformatted text preview: nics, National Chiao Tung University • The cell layer adds more hardware details such as interface width, handshake scheme, wiring constraints, and a clock to the system. • A cell is the basic unit of information, transferred on rising CLOCK edges under the VAL-ACK handshake protocol, defined by the cell layer. Multiple cells constitute a packet. • Both request and response packets are transferred as series of cells on the VCI. The number of cells in a packet depends on the packet length and the interface width. 18/142 BVCI Operations Institute of Electronics, National Chiao Tung University • The basic transfer mechanism in VCI is packet transfer. A packet is sent as a series of cells with the EOP field in the last cell set to value 1. Each cell is individually handshaken under the VAL-ACK handshake. Either the initiator or the target can insert wait cycles between cell transfers by de-asserting VAL or ACK. • Transfer Requests – Read/Write a cell – Read/Write a packet from random/contiguous addresses – Read/Write a packet from one address – Issue a chain of packets • Transfer Responses – Read/Write cell/packet successful – Read/Write packet general error – Read/Write bad data error – Read/Write Abort disconnect 19/142 Advanced VCI Institute of Electronics, National Chiao Tung University • AVCI supports out-of-order transactions and an advanced packet model • Advanced Packet Model – Request and response packets do not have the same size – Need • request packet: one cell, set the start address and address behavior • response packet: many cells, read data return • Arbitration hiding – pipelines of both the request and response packets • Source Identification – a unique identifier for each initiator 20/142 AVCI Protocol Institute of Electronics, National Chiao Tung University • Still 3 layers similar to BVCI. No difference in the transaction layer, slightly differ in the packet and cell layers • Packet layer • Cell layer – AVCI cell layer differs from BVCI with some additional fields, with side band signals for arbitration hiding – Arbitration hiding signals are separately handshaken 21/142 Outline Institute of Electronics, National Chiao Tung University • VCI Interface Standards • AMBA - On Chip Buses • AMBA 3.0 - AXI 22/142 ARM OCB - AMBA Institute of Electronics, National Chiao Tung University • Advanced Microcontroller Bus Architecture (AMBA) • AMBA 2.0 specifies – – – – the Advanced High-performance Bus (AHB) the Advanced System Bus (ASB) the Advanced Peripheral Bus (APB) test methodology ARM Core EBI/TIC On-Chip RAM AHB/ASB DMA Master UART PIO APB Bridge Timer Keypad A typical AMBA system 23/142 Features of AMBA Institute of Electronics, National Chiao Tung University • AHB is superior to ASB in – performance and synthesizibility and timing verification Advanced High-performance Bus (AHB) High performance Pipelined operation Multiple bus master Burst transfers A single centralized decoder Advanced System Bus (ASB) High performance Pipelined operation Multiple bus master Burst transfers A single centralized decoder Advanced Peripheral Bus (APB) Low power Simple interface APB access MUST take 2 PLCK cycles Split transactions single-cycle bus master handover single-clock edge operation non-tristate implementation wider data bus configurations (8/16/32/64/128 bits) 24/142 Notes on the AMBA Specification Institute of Electronics, National Chiao Tung Unive...
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