Electronics national chiao tung university master

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Unformatted text preview: ty • Initiate read and write by providing an address and control interface • Processor, DMA, DSP test interface 33/142 AHB Slave Institute of Electronics, National Chiao Tung University • Respond to a read or write operation within a given address-space range • Back to the master the success, failure or waiting HPROT[3:0] HREADY_in 34/142 Basic Transfer Institute of Electronics, National Chiao Tung University Master action Slave action Drive action Sample action Address & Control A Data & Response B C D A B C D • Address phase : one cycle Data phase : one or several cycles • 1st clock : master drives address and control • 2nd clock : slave samples address and control • 3rd clock : bus master sample the slave’s response 35/142 Multiple Transfers • Three transfers to run related address A, B, and C Institute of Electronics, National Chiao Tung University Address & control Data & Response A B A 1 wait cycle for address B C B C 36/142 Transfer Type (1/2) Institute of Electronics, National Chiao Tung University HTRANS[1:0] 00 Type IDLE Descripton 01 BUSY Masters cannot take next trnsfer place immediately during a burst transfer. Slaves take actions as they take for IDLE. 10 NONSEQ Indicates the first transfer of a burst or a single transfer 11 SEQ Slaves must always provide a zero wait state OKAY response to IDLE transfers and the transfer should be ignored by the slave The remaining transfers in a burst are SEQUENTIAL. The control information is identical to the previous transfer. 37/142 Transfer Type (2/2) Institute of Electronics, National Chiao Tung University • • During T2-T3, master is unable to perform the second transfer of burst immediately and therefore the master uses BUSY transfer to delay the start of the next transfer. During T5-T6, slave is unable to complete access immediately, and uses HREADY to insert a single wait state. 38/142 Burst Operation Institute of Electronics, National Chiao Tung University • 4-, 8-, 16-beat • e.g., 4-beat, start address 0x34, wrapping burst four transfers: 0x34, 0x38, 0x3C, 0x30 • Burst length HBURST[1:0] Type Descripton 000 SINGLE Single Transfer 001 INCR Incrementing burst of unspecified length 010 011 WRAP4 INCR4 4-beat wrapping burst 4-beat incrementing burst 100 WRAP8 INCR8 WRAP16 INCR16 0x38 0x3C 16-beat wrapping burst 111 0x34 8-beat incrementing burst 110 0x30 8-beat wrapping burst 101 WRAP4 16-beat incrementing burst 0x40 0x44 • Limitation: bursts must not cross a 1k Byte address boundary 39/142 Four-beat Wrapping Burst Institute of Electronics, National Chiao Tung University 40/142 Control Signals Institute of Electronics, National Chiao Tung University • Have exactly the same timing as the address bus • Must remain constant throughout a burst of transfers • Types – HWRITE – HSIZE[2:0] – HPROT[3:0]) : Transfer direction : Transfer size : Protection control indicate if the transfer is: • An opcode fetch or data access • A privileged mode access or user mode access • Access is cacheable or bufferable (for bus masters with a memory management unit) 41/142 Transfer Responses (from slave) Institute of Electronics, National Chiao Tung University HPROT[3:0] HREADY_in 42/142 Transfer Responses Institute of Electronics, National Chiao Tung University • HREADY • HRESP[1:0] 00 01 10 11 Response OKAY ERROR RETRY SPLIT • Two-cycle response – ERROR & RETRY & SPLIT – To complete current transfer, master can ta...
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This note was uploaded on 08/23/2009 for the course IEE 5016 taught by Professor Tian-sheuanchang during the Spring '05 term at National Chiao Tung University.

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