Maximum flexibility in allocating the signal timing

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Unformatted text preview: rsity • Technology independence – The specification only details the bus protocol at the clock cycle level • Electrical characteristics – No information regarding the electrical characteristics is supplied • Timing specification – The system integrator is given maximum flexibility in allocating the signal timing budget amongst the various modules on the bus – More free, but may also be more danger and timeconsuming 25/142 Notes on AMBA (1/3) Institute of Electronics, National Chiao Tung University • Split transaction – NOT truly split transaction - the arbiter only masks the access of the master which gets a SPLIT transfer response – Master does not need extra slave interface – Only allows a single outstanding transaction per bus master • NOT support Sideband signals – Sideband signals: reset, interrupts, control/status, generic flags, JTAG test interface, etc. – Require the system integrator to deal with them in an ad-hoc way for each system design. – Good references of sideband signals: VSIA VCI or Sonics OCP OCP: Open Core Protocol 26/142 Notes on AMBA (2/3) Institute of Electronics, National Chiao Tung University • DMA channels – Use AHB protocol • E.g. PrimeCell SDRAM Controller • Easy to connect to another AHB bus – Adopt user defined protocol • Lower the complexity of the DMA interface 27/142 Notes on AMBA (3/3) Institute of Electronics, National Chiao Tung University • APB does not support WAIT transaction – Access status register first, then access data register – Alternative: designed as AHB slaves – Multiple AHB/APB to reduce loading Wipro’s SOC-RaPtorTM Architecture 28/142 AHB Interconnect Institute of Electronics, National Chiao Tung University • Bus master drives the address and control • Arbiter selects one of the master 29/142 AHB Operation (1/2) Institute of Electronics, National Chiao Tung University • Master asserts a request signal to the arbiter. Arbiter then gives the grant to the master. • A granted bus master starts an AHB transfer by driving WRAP4 address and control signals: 0x10 – – – – address direction width burst forms • Incrementing burst: not wrap at address boundaries • Wrapping burst: wrap at particular address boundaries • Write data bus: move data from the master to a slave • Read data bus: move data from a slave to the master 0x14 0x18 0x1C 0x20 0x24 INCR4 Address wrap in 4word boundary 30/142 AHB Operation (2/2) Institute of Electronics, National Chiao Tung University • All slaves sample the address Data can be extended using the HREADY signal, when LOW, wait states be inserted and allow extra time for the slave to provide or sample data • During a transfer the slave shows the status using the response signals HRESP[1:0] – OKAY: transfer progressing normally when HREADY is HIGH, transfer has completed successfully – ERROR: transfer error – RETRY and SPLIT: transfer can’t complete immediately, but the bus master should continue to attempt the transfer • As burst transfer, the arbiter may break up a burst and in such cases the master must re-request for the bus. 31/142 Address Decoding Institute of Electronics, National Chiao Tung University • A central address decoder provides HSELx for each slave • Minimum address space that can be allocated to a single slave is 1K Byte – No incrementing transfers can over a 1K Byte boundary 32/142 AHB Master Institute of Electronics, National Chiao Tung Universi...
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