Performance 45142 narrow slave on a wide bus

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: ke following action Cancel for RETRY Cancel for SPLIT Either cancel or continue for ERROR 43/142 Examples of Two-cycle Response • Retry response Institute of Electronics, National Chiao Tung University Cancel • Error response Wait Error Error 44/142 Data Buses Institute of Electronics, National Chiao Tung University • HWDAA : 32 bits • RDATA : 32 bits • Endianness : fixed, lower power; higher performance 45/142 Narrow Slave on A Wide Bus Institute of Electronics, National Chiao Tung University 46/142 Wide Slave on A Narrow Bus Institute of Electronics, National Chiao Tung University 47/142 Arbitration Institute of Electronics, National Chiao Tung University 48/142 Granting Bus Access With No Wait States Institute of Electronics, National Chiao Tung University 49/142 Granting Bus Access Institute of Electronics, National Chiao Tung University Last Transfer of last bus owner Wait Wait 50/142 Bus Master Grant Signals Institute of Electronics, National Chiao Tung University Arbiter 51/142 Split Transfer HREADY_in Institute of Electronics, National Chiao Tung University HPROT[3:0] 52/142 Split Transfer Institute of Electronics, National Chiao Tung University 53/142 AHB-Lite • Requirement Institute of Electronics, National Chiao Tung University – Only one master – Slave must not issue Split or Retry response • Subset of AHB Functionality – Master: no arbitration or Split/Retry handling – Slave: no Split or Retry responses • Standard AHB masters can be used with AHB-Lite • Advantage – Master does not have to support: the following cases: • Losing bus ownership • Early bus termination • Split and Retry response – No arbiter – No Master-to-slave mux – Allows easier module design/debug 54/142 AHB-Lite Interchangeability Institute of Electronics, National Chiao Tung University 55/142 AHB-Lite Master Institute of Electronics, National Chiao Tung University 56/142 AHB-Lite Slave HREADY_in Institute of Electronics, National Chiao Tung University HPROT[3:0] 57/142 Multi-layer AHB (1/2) Institute of Electronics, National Chiao Tung University Master #1 Interconnect Matrix Slave #1 Slave #2 Master #2 Slave #3 Master #3 Slave #4 58/142 Multi-layer AHB (2/2) Institute of Electronics, National Chiao Tung University • • • Local slaves Multiple slaves on one slave port Multiple masters on one layer Mixed implementation of AHB and AHB-Lite in a multi-layer system. 59/142 Comparison among AMBA and other OCBs OPB Institute of Electronics, National Chiao Tung University Width (bits) PLB APB ASB Mbus PalmBus FISPbus 8, 16, 32 8, 16, 32,64 8, 16, 32,64 8, 16, 32 1 Data Tranfer 1 Data Tranfer Data Bus Width Data Bus Width Symbolic Symbolic Symbolic early, term term term middle. late early, middle. late AHB 8, 16, 32 32 2.9 GB/s, up to 32 8, 16, 32 2n, 183 MHz bit n=3~10 128 bit Peak Bandwidth (size/per cycle) 1 Data Tranfer Timing Guidelines % 2 Data Tranfer Synchronous Data Bus Distribu Multiple Implementation ted And- xor Or/ Multiple xor 4 bytes 0.5 bus width % 4 bytes 1 bus width rising clock edge falling clock edge* PIbus Plbus2 1 bus width rising c...
View Full Document

Ask a homework question - tutors are online