Poor read data setup break long interconnect path r

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Unformatted text preview: nel delay • Allows system topology to be matched to performance requirements Source: First details of AXI, ARM 73/142 Example Register Slices A Institute of Electronics, National Chiao Tung University R A Master #1 R Isolate address timing A R A Master #2 Slave #1 Slave #2 A R R Slave #3 A Isolate poor read data setup Break long interconnect path R Slave #4 Source: First details of AXI, ARM 74/142 AMBA 2.0 AHB Burst Institute of Electronics, National Chiao Tung University ADDRESS A11 DATA A12 A13 A14 A21 A22 A23 D31 D11 D12 D13 D14 D21 D22 D23 D31 • AHB Burst – Address and Data are locked together – Single pipeline stage – HREADY controls intervals of address and data Source: First details of AXI, ARM 75/142 AXI - One Address for Burst Institute of Electronics, National Chiao Tung University ADDRESS A11 DATA A21 D11 D12 D13 D14 D31 D21 D22 D23 D31 • AXI Burst – One Address for entire burst Source: First details of AXI, ARM 76/142 AXI - Outstanding Transactions Institute of Electronics, National Chiao Tung University ADDRESS A11 DATA A21 D31 D11 D12 D13 D14 D21 D22 D23 D31 • AXI Burst – One Address for entire burst – Allows multiple outstanding addresses Source: First details of AXI, ARM 77/142 Out of Order Interface Institute of Electronics, National Chiao Tung University • Each transaction has an ID attached – Channels have ID signals - AID, RID, etc. • Transactions with the same ID must be ordered • Requires bus-level monitoring to ensure correct ordering on each ID – Masters can issue multiple ordered addresses Source: First details of AXI, ARM 78/142 AMBA 2.0 AHB Burst - Slow slave Institute of Electronics, National Chiao Tung University ADDRESS A11 A12 A13 A14 A21 A22 A23 DATA D31 D11 D12 • With AHB – If one slave is very slow, all data is held up. Source: First details of AXI, ARM 79/142 AXI - Out of Order Completion Institute of Electronics, National Chiao Tung University ADDRESS DATA A11 A21 D31 D21 D22 D23 D31 D11 D12 D13 D14 – Out of order completion allowed – Fast slaves may return data ahead of slow slaves – Complex slaves may return data out of order Source: First details of AXI, ARM 80/142 AXI - Data Interleaving Institute of Electronics, National Chiao Tung University ADDRESS DATA A11 A21 D31 D21 D22 D11 D23 D12 D31 D13 D14 – Returned data can even be interleaved – Gives maximum use of data bus – Note - Data within a burst is always in order Source: First details of AXI, ARM 81/142 AXI Multi-layer Institute of Electronics, National Chiao Tung University • Parallel paths between masters and slaves • Key Advantages – Increased bandwidth – Design flexibility • Uses the same interface protocol Master Master #1 #1 Master Master #2 #2 Bus Bus Matrix Matrix Slave Slave #1 #1 Slave Slave #2 #2 Slave Slave #3 #3 Master Master #3 #3 Slave Slave #4 #4 Source: First details of AXI, ARM 82/142 Summary Institute of Electronics, National Chiao Tung University • AXI is the next generation AMBA bus – – – – – Channel architecture Registers Slices Burst addressing Multiple outstanding bursts Out of order completion • Interconnect Options – Shared bus, multi-layer and mixed 83/142...
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This note was uploaded on 08/23/2009 for the course IEE 5016 taught by Professor Tian-sheuanchang during the Spring '05 term at National Chiao Tung University.

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