04_SOC_Design_Process - SOC Design Process SOC Design...

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Unformatted text preview: SOC Design Process SOC Design Process Tian-Sheuan Chang SOC Design Process • SOC design flow • System level design issues • Macro design flow SOC Design Process Tian-Sheuan Chang 1 Copyright ©2003 All rights reserved 1. SOC Design Flow • To meet challenges of SOC, design flow changes from – From a waterfall model to a spiral model – From a top-down to a combination of top-down and bottom-up SOC Design Process Tian-Sheuan Chang 2 Copyright ©2003 All rights reserved Traditional ASIC Design Flow • Waterfall model • Recursive Specification Development RTL code development – “From error to where ?” Functional Verification • Verification Strategy Tian-Sheuan Chang SOC Design Process – “Design is becoming COMPLEX !” • Time-To-Market Pressure • What’s the problem – Handoff are rarely clean – Larger, deep submicron designs • co-development for HW and SW • Physical issues 3 Synthesis Timing Verification (VITAL) Place and Route Prototype build and test Deliver to system integration and software test Copyright ©2003 All rights reserved SOC Design Process • Evolution: waterfall to spiral model – Addressing these problems concurrently Tian-Sheuan Chang SOC Design Process • • • • Functionality, Timing, Physical design and Verification – Incrementally improving as design converges • Top-down to combination of top-down and bottom-up – Bottom-up with critical low-level blocks, reuse soft or hard macros 4 Copyright ©2003 All rights reserved Spiral Model Goal : Maintain parallel interating design flows SYSTEM DESIGN AND VERIFICATION PHYSICAL TIMING Timing specification: I/O timing clock frequency Preliminary floorplan Updated floorplans Hardware specification Software specification Algorithm development & macro decompsition Application prototype development Block timing specification Block selection/ Design Application prototype testing Block synthesis Block verification Application development Top-level HDL Application testing Top-level verification Application testing Updated floorplans Trial placement SOFTWARE Top-level synthesis Final place and route Tapeout 5 TIME Tian-Sheuan Chang SOC Design Process Physical specification: area, power, clock tree design HARDWARE Copyright ©2003 All rights reserved Waterfall v.s. Spiral • Waterfall • Sprial – For large, deep submicron designs – Parallel development of H/W & S/W – Parallel verification and synthesis – Floorplaning and P & R in synthesis process – Use predesigned Macros (Hard/Soft) – Planned iteration throughput – Work well up to 100K gate and down .5u – Serial H/W and S/W development SOC Design Process Tian-Sheuan Chang “H/W and S/W development concurrently : functionality, timing, physical design, and verification” 6 Copyright ©2003 All rights reserved Top-Down vs. Bottom-Up • Classical top-down – Begin with spec and decomposition – End with integration and verification – Assuming lowest level block, pre-designed • Too ideal to be easily broken and cause unacceptable iteration Tian-Sheuan Chang SOC Design Process • Real-world design team – Mixture of top-down and bottom-up design – Building critical low-level blocks early – Libraries of reusable hard and soft macros helps this process 7 Copyright ©2003 All rights reserved “Construct by Correction” • Construct by correction – Made the first pass ASAP, and refine later – Why • allow for multiple iterations – Used in Sun Microsystem’s UltraSPARC design methodology • “One of the most successful in Sun Microsystem’s History” Tian-Sheuan Chang SOC Design Process – Take from architecture definition through P & R – Foresee impact of architectural decision on final design: area, power, performance – Target • larger, complex designs • Correction by construct – Make the first pass completely right – Target • small designs 8 Copyright ©2003 All rights reserved Key to SOC Design Process • Iteration is an inevitable part of the design process • The problem is how large the loop is • Goal – Minimize the overall design time • But How Tian-Sheuan Chang SOC Design Process – Planned for iterations – Minimize iteration numbers • especially major loops (Spec to chip) – Local loop is preferred • coding, verifying, synthesizing small blocks – IP clearly help due to pre-verified – Parameterized blocks offer more tradeoff between area, performance and functionality • Carefully designed spec is the best way to minimize the loops 9 Copyright ©2003 All rights reserved Specification Problems • First part of design process – Most crucial, challenging, lengthy phase of project • Why it is so important – Specification is your destination Tian-Sheuan Chang SOC Design Process • If you know it exactly, you can spot the error path and fix it quickly • If not, you may not spot major errors until late • Now the question – When shall you document your specification • Early phase in the design cost less and more valuable • Later phase may only delays the project or be skipped 10 Copyright ©2003 All rights reserved Purpose of Specification • Specification for Integration Tian-Sheuan Chang SOC Design Process – – – – – – Functional/Physical/ Design requirements The block diagram Interfaces to external system Manufacturing test methodology Software model Software requirements • Specification for block Design – – – – – – Algorithm spec Interface spec Authoring guide Test Spec – lint & coverage Synthesis constraints Verification environment, tools used 11 Copyright ©2003 All rights reserved Types of Specifications • Written in natural language – Traditional, ambiguous, incompleteness, erroneous • Formal specification Tian-Sheuan Chang SOC Design Process – Desired characteristic (functionality, timing, power, area,…), independent to implementation – Not widely used, important research topic • Executable specification – Description of functional behavior – Parallel with RTL Model in the TestBench 12 Copyright ©2003 All rights reserved Executable Specification • Procedural language for behavioral modeling – Design productivity • Easy to model complex algorithm • Fast execution • Simple testbench Tian-Sheuan Chang SOC Design Process – Tools • Native C/C++ through PLI/FLI • Extended C/C++ : SpecC, SystemC • Verify it on the fly! – Test vector generation – Compare RTL code with behavioral model – Coverage test 13 Copyright ©2003 All rights reserved Using Executable Specifications • Ensure completeness of specification – Even components(e.g. peripherals) are so complex – Create a program that behave the same way as the system • Avoid unambiguous interpretation of the specification Tian-Sheuan Chang SOC Design Process – Avoids unspecified parts and inconsistencies – IP customer can evaluate the functionality up-front • Validate system functionality before implementation – Early feedback from customer – Create early model and validate system performance • Refine and test the implementation of the specification – Test automation improves time-to-market 14 Copyright ©2003 All rights reserved Executable Spec Motivation Customer System Verification, Error Checking Bottleneck Customer System Tian-Sheuan Chang SOC Design Process Paper Spec Executable Spec HDL Design HDL Design Netlist HDL TestBench with C-Interface (PLI/FLI) Netlist Layout Layout Silicon Silicon 15 Copyright ©2003 All rights reserved Time Spent in Design Phases Conventional methodologies Tian-Sheuan Chang SOC Design Process Time Spent Debugging Product Planning System Design Logic Design 14% 12% Physical Design & Assembly 18% 20% Product Requirements Mis-communicated By customer 13% 50% Specification incorrectly Translated or ambiguous Prototype Debug 43% 30% Incorrect Login in Design Source: Toshiba/Collet/STOC 16 Copyright ©2003 All rights reserved Specification Based Design C/C++ System Level Model conversion HDL Simulation Executable Spec. refine Analysis Tian-Sheuan Chang SOC Design Process Results Test Bench C-to-HDL Paper Spec. Interface (PLI/FLI) •Manual Test Vector conversion (VCD/WAVES) creates errors •Disconnect Waveform between SCompare ystem Model and HDL Synthesis Netlist Simulation P&R Netlist Simulation Silicon 17 Copyright ©2003 All rights reserved System Design Process IDENTITY system requirements WRITE preliminary specifications DEVELOP high-level algorithmic model C/C++/MATLAB/SES/ NuThena/Bones/COSSAP REFINE and TEST algorithms C/C++/COSSAP/SPW/SDL Tian-Sheuan Chang SOC Design Process DETERMINE hardware/software partition Characterized library of hardware/software macros & interface protocols WRITE WRITE hardware specification software specification DEVELOP behavioral model for hardware DEFINE interfaces DEVELOP prototype of software PARTITION DEVELOP into macros software Macro 1 ... hardware/software Macro n COSIMULATION WRITE preliminary specification for macro 18 Copyright ©2003 All rights reserved SoC Design Characteristics • Design Level – RTL / Behavioral > Architectural / VC Evaluation • Design Team – Small, Focused > Multidisciplinary> Multi-Group, Multidisciplinary • Primary Design Tian-Sheuan Chang SOC Design Process – Custom Logic > Blocks, Custom Interface> Interface to System / Bus • Design Reuse – Opportunistic Soft, Firm and Hard > Planned Firm and Hard • Optimization Focus – Synthesis, Gate-level > Floor planning, Block Architecture > System Architecture 19 Copyright ©2003 All rights reserved SoC Test Characteristics • Test Architecture – Scan/JTAG/BIST/Custom > Hierarchical, Parallel scan/JTAG/BIST/custom • Bus Architecture – Custom > Standardized / Multiple app-specific Tian-Sheuan Chang SOC Design Process • Verification Level – Gate/RTL > Bus functional/RTL/Gate > Mixed (ISS to RTL with H/W and S/W) • Partitioning Focus – Synthesis limitation > Functions / Communication 20 Copyright ©2003 All rights reserved SoC Layout Characteristics • Placement – Flat > Flat with limited hierarchical > Hierarchical • Routing – Flat > Flat with limited hierarchical > Hierarchical Tian-Sheuan Chang SOC Design Process • Timing – Flat > Flat with limited hierarchical > Hierarchical • Physical Verification – Flat > Flat with limited hierarchical > Hierarchical 21 Copyright ©2003 All rights reserved Transition of SoC Design Methodology • From area-driven to timing-driven design • From block-based to platform-based design SRAM uP Core Flash Tian-Sheuan Chang SOC Design Process uP Core SRAM Logic ADD TDD FIFO ROM Serial MMC I/F Logic MPEG Logic Logic SRAM ROM USB Soft I/F IP BBD PBD Design Methodology 22 Copyright ©2003 All rights reserved SoC Design Methodology • Transition of Design Methodology – ADD > TDD > BBD > PBD • Reuse-the key to SoC design – Personal > Source > Core > Virtual Component Tian-Sheuan Chang SOC Design Process • Integration approach – IP-Centric vs. Integration-Centric Approach • SoC and productivity – Executable specification • Test automation • Real-world stimuli • Higher-level algorithmic system modeling 23 Copyright ©2003 All rights reserved 2. System-Level Design Issues Key Aspects of Design Reuse • Fundamentals – Well-designed IP is the key to successful SOC design • System level design guidelines Tian-Sheuan Chang SOC Design Process – To produce well-designed IP – To integrate well-designed IP to an SOC design – Driven by the needs of IP integrator and chip designer • Principles behind these guidelines – Discipline • Consistent good practices – Simplicity • The simpler the design, the easier to fix the bugs – Locality • Make timing and verification problem local by careful block and interface design 24 Copyright ©2003 All rights reserved Full Custom Design in Reuse • Full custom design – Design that are not from synthesis • Major problems Tian-Sheuan Chang SOC Design Process – Performance gain is limited – Non-portable, hard to modify designs – Redesign take time • Limit full custom design for only small part of design – Even aggressive processor designer uses full custom only for data path 25 Copyright ©2003 All rights reserved Interface and Timing Closure • Timing problems due to deep submicron process – Dominated wire delay – Imprecise wireload model due to uncertainty of wire delays • Solution – Tools Tian-Sheuan Chang SOC Design Process • Timing driven P&R, Physical synthesis – Tactics for fundamental good design • Register all inputs/outputs of the macro – Unit for floorplan • Register all outputs of the subblock of macro – Unit for synthesis • Exception – Cache interface – Design likes PCI interface that needs glue logic at the interface 26 Copyright ©2003 All rights reserved Synchronous v.s. Asynchronous • Synchronous – Avoid asynchronous and multi-cycle paths – Tools work best for synchronous design • Accelerate synthesis and simulation – Ease static timing analysis Tian-Sheuan Chang SOC Design Process • Register based – Use (positive) edge triggered DFF – Latches shall be used only in small memory or FIFOs 27 Copyright ©2003 All rights reserved Clocking • Clock planning – – – – Minimize the number of clock domains Isolate the interface between clock domains Careful synchronizer design to avoid metastability Isolate clock generation and control logic • Document the clock scheme Tian-Sheuan Chang SOC Design Process – Required clock frequencies and PLL – Interface timing requirements to other parts of the system • PL L – Disabling/bypassing scheme – Ease testing • For hard blocks – Eliminate the clock delay using a PLL – Balance the clock insertion delay 28 Copyright ©2003 All rights reserved Reset • Synchronous reset – Easy to synthesize – Requires a free-running clock • Asynchronous reset SOC Design Process Tian-Sheuan Chang – – – – – Do not require a free-running clock Not affect flip-flop data timing due to separated input Harder to implement, like clock, CTS is required Synchronous de-assertion problem Make STA and cycle-based simulation more difficult • Asynchronous reset is preferred 29 Copyright ©2003 All rights reserved Internal Generated Reset • Internal generated reset causes unwanted reset during scan shift • Solution Tian-Sheuan Chang SOC Design Process – Force internal generated reset signal inactive during test power-on reset FF FF reset to all FF test_mode_n 30 Copyright ©2003 All rights reserved Design for Verification Tian-Sheuan Chang SOC Design Process • Principle of locality • Plan before design starts • Testbenches should reflect the system environment • Best strategy – Bottom-up verification – Challenges: developing testbench – Solution • Macros with clean, well-designed interface • High level verification languages + code coverage tool 31 Copyright ©2003 All rights reserved System Interconnection • Tri-state bus is not good – Bus contention problem • Reduce reliability • One and only one driver at a time – Harder for deep submicron design Tian-Sheuan Chang SOC Design Process – Bus floating problem • Reduce reliability • Bus keeper – ATPG problem – FPGA prototyping problem • Multiplexer-based bus is better 32 Copyright ©2003 All rights reserved IP-to-IP Interface • Direct connection (via FIFO) – – – – Tian-Sheuan Chang SOC Design Process Higher bandwidth Redesign for different IP Become unmanageable when the IP number increases Only suitable for design connected to analog block, e.g. PHY • Bus-based – – – – Eliminate direct link Layered approach can offer higher bandwidth All IPs talk to bus only, thus only IP-to-bus problem The mainstream of current IP-based SOC integration • Choose the standard bus whenever possible 33 Copyright ©2003 All rights reserved On-chip Bus (OCB) • ARM AMBA – – – – Advanced Microcontroller Bus Architecture Dominant player V 3.0 is on the road Available solution Tian-Sheuan Chang SOC Design Process • Synopsys DW_AMBA, … • • • • • Sonics OCP VSIA OCB 2.1 WishBone Silicore IBM CoreConnect …. 34 Copyright ©2003 All rights reserved AMBA Bus System SOC Design Process Tian-Sheuan Chang 35 Copyright ©2003 All rights reserved Design for Debug: On-chip Debug • Experienced teams assume chip won’t work when first power up and plan accordingly. • Challenges for IP test Tian-Sheuan Chang SOC Design Process – IPs are deeply embedded within the SOC design – Disaster to the system and S/W engineers • Solution – Principle: increase controllability and observability – Add debug support logic to the hardware – MUX bus to existing I/O pins 36 Copyright ©2003 All rights reserved Low Power (1/3) P = ∑ αCV 2 f α : switching activity, C : capacitanc e, V : supply voltage, f : frequency • Reduce the supply voltage – Process improvement • Reduce capacitance Tian-Sheuan Chang SOC Design Process – Low power cell and I/O library – Less logic for the same performance • Reduce switching activity – Architecture and RTL exploration – Power-driven synthesis – Gate-level power optimization 37 Copyright ©2003 All rights reserved Low Power (2/3) • Memory – – – – Dominated power consumption Low-power memory circuit design Partition a large memory into several small blocks Gray-coded address interface Tian-Sheuan Chang SOC Design Process 32KB 64KB 32KB 38 Copyright ©2003 All rights reserved Low Power (3/3) • Clock gating – 50% - 70% power consumed in clock network reported – gating the clock to an entire block Block A Clock – gating the clock to a register Tian-Sheuan Chang SOC Design Process generation and gating always @(posedge clk) if(en) q <= q_nxt; Block B DQ en clk assign clk1 = clk & en; always @(posedge clk1) q <= q_nxt; DQ en clk 39 Copyright ©2003 All rights reserved Design for Test • Memory test – Memory BIST is recommended • Processor test Tian-Sheuan Chang SOC Design Process – Chip level test controller (including scan chain controller and JTAG controller) – Use shadow registers to facilitate full-scan testing of boundary logic • Other macros – Full scan is strongly recommended • Logic BIST – Embedded stimulus generator and response checker – Not popular yet 40 Copyright ©2003 All rights reserved 3. Macro Design Process • • • • Top-level macro design Subblocks design Integrate subblocks Macro productization SOC Design Process Tian-Sheuan Chang 41 Copyright ©2003 All rights reserved Problem in SoC Era • Productivity gap • Time-to-market pressure • Increasing design complexity Tian-Sheuan Chang SOC Design Process – – – – HW/SW co-development System-level verification Integration on various levels and areas of expertise Timing closure due to deep submicron Solution: Platform-based design with reusable IPs 42 Copyright ©2003 All rights reserved Design for Reuse IPs • Design to maximize the flexibility – configurable, parameterizable • Design for use in multiple technologies Tian-Sheuan Chang SOC Design Process – synthesis script with a variety of libraries – portable for new technologies • Design with complete verification process – robust and verified • Design verified to a high level of confidence – physical prototype, demo system • Design with complete document set 43 Copyright ©2003 All rights reserved Parameterized IP Design • Why to parameterize IP? – Provide flexibility in interface and functionality – Facilitate verification • Parameterizable types Tian-Sheuan Chang SOC Design Process – Logic/Constant functionality – Structural functionality • Bit-width、depth of FIFO、regulation and selection of submodule – Design process functionality (mainly in test bench) • Test events • Events report (what, when and where) • Automatic check event – Others (Hardware component Modeling, 1996) Authors: Vicktor Preis and Sabine Marz-Rossel, Modeling Highly Flexible and Self-generating Parameterizable Components In VHDL 44 Copyright ©2003 All rights reserved Collected in book "Hardware component Modeling", 1996, by Jean-Michel Berge, Oz Levia and Jacques Rouillard IP Generator/Compiler • User specifies Tian-Sheuan Chang SOC Design Process – Power dissipation, code size, application performance, die size – Types, numbers and sizes of functional unit, including processor – User-defined instructions. • Tool generates – RTL code, diagnostics and test reference bench – Synthesis, P&R scripts – Instruction set simulator, C/C++ compiler, assembler, linker, debugger, profiler, initialization and self-test code 45 Copyright ©2003 All rights reserved Logic/Constant Functionality • Logic Functionality • Constant Functionality SOC Design Process Tian-Sheuan Chang – Synthesizable code always @(posedge clock) begin if (reset==`ResetLevel) begin … end else begin … end end – Synthesizable code assign tRC_limit= (`RC_CYC > (`RCD_CYC + burst_len)) ? `RC_CYC - (`RCD_CYC + burst_len) : 0; – For test bench always #(`T_CLK/2) clock = ~clock; … initial begin #(`T_CLK) event_1; #(`T_CLK) event_2; … end 46 Copyright ©2003 All rights reserved Reusable Design - Test Suite • Test events – Automatically adjusted when IP design is changed – Partition test events to reduce redundant cases when test for all allowable parameter sets at a time • Debug mode Tian-Sheuan Chang SOC Design Process – – – – Test for the specific parameter set at a time Test for all allowable parameter sets at a time Test for the specific functionality Step control after the specific time point • Display mode of automatic checking – – – – display[0]: event current under test display[1]: the time error occurs display[2]: expected value and actual value ... 47 Copyright ©2003 All rights reserved Reusable Design - Test Bench • Use Global Connector to configure desired test bench – E.g.: bus topology of IEEE 1394 Tian-Sheuan Chang SOC Design Process Device 0 Device 0 Device 3 Device 3 Device 1 Device 1 Device 2 Device 2 48 Copyright ©2003 All rights reserved Characteristics of Good IP • • • • Configurability Standard interface Compliance to defensive design practices Complete set of deliverables SOC Design Process Tian-Sheuan Chang – – – – Synthesizable RTL Verification suite Related scripts of EDA tools Documentations 49 Copyright ©2003 All rights reserved IP Core Macro Design Process Block specification DEVELOP functional specification Completed behavioral model for HW/SW cosimulation and test development DEVELOP behavioral model DEVELOP testbench TEST behavioral model CERATE BEHAVIROAL MODEL Tian-Sheuan Chang SOC Design Process PARTITION design into subblocks WRITE functional specification WRITE technical specification DEVELOP timing constraints WRITE RTL RUN Lint SYNTHESIS PERFORM power analysis Meets timing, power, & area requirements DEVELOP testbench Perform these steps for each subblock SIMULATE MEASURE test coverage Coverage tool passes PASSES - READY FOR INTEGRATION Source: Michael Keating and Pierrr Bricaud, Reuse Methodology ©2003 2nd ed. 1999. 50 Copyright Manual, All rights reserved Macro Integration Process Subblock 1 Subblock 1 Subblock 1 DETERMINE configuration and GENERATE top-level HDL Top-level HDL FUNCTIONAL VERIFICATION with reference simulator GENERATE synthesis scripts RUN lint Tian-Sheuan Chang SOC Design Process SYNTHESIZE with reference library DEVELOP and RUN multiple configuration tests MEASURE test coverage Scan insertion, ATPG, fault simulation PERFORM final timing and power analysis READY FOR PRODUCTION PRODUCTIZE as soft macro PRODUCTIZE as hard macro Source: Michael Keating and Pierrr Bricaud, Reuse Methodology ©2003 2nd ed. 1999. 51 Copyright Manual, All rights reserved Four Major Phases • Design top-level macro – macro specification; behavior model – macro partition • Design each subblock Tian-Sheuan Chang SOC Design Process – specification and design – testbench; timing, power check • Integration subblocks • Macro productization 52 Copyright ©2003 All rights reserved Specification at Every Level SOC Design Process Tian-Sheuan Chang • • • • • • • • • • • Overview Functional requirements Physical requirements Design requirements Block diagram Interface to external system Manufacturing test methodology Software model Software requirement Deliverables Verification 53 Copyright ©2003 All rights reserved Top-Level Macro Design Flow Macro specification DEVELOP detailed technical specification Tian-Sheuan Chang SOC Design Process CODE behavioral model C/Verilog/VHDL CODE testbench C/Verilog/VHDL/Vera/Specman Completed behavioral model for HW/SW cosimulation and test development TEST behavioral model CERETE BEHAVIROAL MODEL PARTITION the block into subblocks Source: Michael Keating and Pierrr Bricaud, Reuse Methodology Manual, 2nd ed. 1999. 54 Copyright ©2003 All rights reserved Top-Level Macro Design • Updated macro hardware specification – document • Executable specification Tian-Sheuan Chang SOC Design Process – language description – external signals, timing – internal functions, timing • Behavioral model – SystemC, HDL • Testbench – test vector generation, model for under test unit, monitoring and report • Block partition 55 Copyright ©2003 All rights reserved Subblock Design Flow WRITE functional specification WRITE technical specification Tian-Sheuan Chang SOC Design Process DEVELOP timing constraints WRITE RTL RUN Lint DEVELOP testbench SIMULATE Verilog/VHDL SYNTHESIS Design Compiler PERFORM power analysis PowerCompiler/QuickPower Meets timing, power, & area requirements MEASURE testbench coverage VHDLCover/VeriSure/CoverMeter Coverage tool passes PASSES - READY FOR INTEGRATION Source: Michael Keating and Pierrr Bricaud, Reuse Methodology ©2003 2nd ed. 1999. 56 Copyright Manual, All rights reserved Subblock Design • Design elements Tian-Sheuan Chang SOC Design Process – – – – – Specification Synthesis script Testbench Verification suite RTL that pass lint and synthesis 57 Copyright ©2003 All rights reserved Linter • Fast static RTL code checker – preprocessor of the synthesizer – RTL purification • syntax, semantics, simulation Tian-Sheuan Chang SOC Design Process – timing check – testability checks – reusability checks • Shorten design cycle by avoiding lengthy iterations 58 Copyright ©2003 All rights reserved Subblock Integration Flow Subblock 1 Subblock 1 Subblock 1 DETERMINE configuration and GENERATE top-level HDL Top-level HDL FUNCTIONAL VERIFICATION Verilog/VHDL simulator ModelSim, VSS, VCS RUN lint Verilint, VHDLlint GENERATE top-level synthesis scripts Tian-Sheuan Chang SOC Design Process SYNTHESIZE with reference library Design Compiler Scan insertion, ATPG, coverage analysis Test Compiler, DFTAdvisor, FastScan/FlexTest DEVELOP and RUN multiple configuration tests Verilog/VHDL simulator ModelSim, VSS, VCS PERFORM analysis QuickPower, Power Compiler READY FOR PRODUCTION PRODUCTIZE as soft macro PRODUCTIZE as hard macro 59 Copyright ©2003 All rights reserved Subblock Integration • Integration process is complete when Tian-Sheuan Chang SOC Design Process – top-level RTL, synthesis script, testbench complete – macro RTL passes all tests – macro synthesizes with reference library and meets all timing, power and area criteria – macro RTL passes lint and manufacturing test coverage 60 Copyright ©2003 All rights reserved Macro Productization From block integration DEVELOP specification for prototype chip TRANSLATE Verilog ↔ VHDL SYNTHESIS to multiple technologies REGRESSION TEST on translated code RUN Pre-sim on one technology RUN TESTS on multiple simulators Formal Verification RTL vs. gates DESIGN chip SYNTHESIS chip Tian-Sheuan Chang SOC Design Process Scan insertion, ATPG and coverage analysis CREATE user documents: e.g., user guide Verification guide Integration guide Test guide FLOORPLAN PLACE and ROUTE VERIFY timing FABRICATE TEST chip in demo board Release 61 Copyright ©2003 All rights reserved Soft Macro Production • Produce the following components – Verilog version of the code, testbenches, and tests – Supporting scripts for the design • installation script • synthesis script Tian-Sheuan Chang SOC Design Process – Documentation 62 Copyright ©2003 All rights reserved ...
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