04_Synthesis_guidelines - Synthesis Guidelines Synthesis...

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: Synthesis Guidelines Synthesis Guidelines Tian-Sheuan Chang Macro Synthesis Strategy • Strategy – Top down for designs < 100K gates • simpler – Bottom up for designs > 100K gates • Faster run time • Timing constraints Tian-Sheuan Chang Synthesis Guidelines – Key to successful synthesis and physical design – Start as the part of specification and reviewed regularly – Including • • • • • • Clock definition Setup time for macro synchronous input Clock to output delay for macro synchronous output Input/output delay for all combinational path Input driving and output loading Operating conditions 1 Copyright ©2003 All rights reserved Subblock Synthesis Strategy • Similar guidelines as macro synthesis strategy • Start preliminary synthesis ASAP Tian-Sheuan Chang Synthesis Guidelines – Identify and fix timing problems early – Modify or restructure the RTL according – Target : within 10 ~ 20% of the final timing budget 2 Copyright ©2003 All rights reserved Synthesis Process • Subblock level – – – – Complete each subblock using specified timing Perform characterization for each block Refine the constraints and resynthesize Iterate if required • Macro level Tian-Sheuan Chang Synthesis Guidelines – Top down • Perform characterization on macro using top level constraints • Incremental compile – Bottom up • Compile each subblocks using timing budget • Perform characterization on macro using top level constraints • Incremental compile • Preserve clock and reset networks – Set infinite driving strength 3 Copyright ©2003 All rights reserved Synthesis Related Checking • Before synthesis – Run linter • Unintentional latch, non-synthesizable RTL, incomplete sensitivity list, … – Syntax checking of synthesis script – Elaboration checking Tian-Sheuan Chang Synthesis Guidelines • Types of inferred sequential elements, resource allocations • After synthesis – – – – – Combinational loop checking Latch checking Design rule violation checking Testability checking Equivalence checking • Check equivalence between RTL and synthesized netlist 4 Copyright ©2003 All rights reserved Coding Guidelines for Synthesis Scripts • • • • Header Comments Under revision control system No hard-coded numbers and path – Variables used in the body and values set at the top Tian-Sheuan Chang Synthesis Guidelines • As simple as possible • Common comments reside in a single setup file – Library path,search path… • Thorough test of scripts for parameterized soft macros 5 Copyright ©2003 All rights reserved ...
View Full Document

Ask a homework question - tutors are online