CS312-CH5 - 1 Ch 5 The Processor 5.1 Introduction 5.2...

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Unformatted text preview: 1 Ch 5 The Processor 5.1 Introduction 5.2 Building a Datapath 5.3 A Simple Implementation Scheme 5.4 A multicycle Implementation 2 5.1 Introduction (background) Factors affecting machine performance Instruction Count (I) Clock-cycle Time (t) Cycles per Instruction (CPI) Instruction Count determined by program, compiler and architecture Clock-cycle time and CPI determined by processor implementation 3 5.1 Introduction - goals how to design a datapath and control unit for three classes of instructions: data transfer instructions (lw, sw) arithmetic/logic instructions (add, sub, and, or, slt) conditional/unconditional branch instructions (beq, j) For every instruction 1. Set PC to the memory location containing the next instruction, and fetch it 2. Read one or two registers, based on the instruction 3. Next steps depend on instruction 4 5.1 Introduction what inside the CPU In s tr u c tio n a d d r e s s In s tr u c tio n a . In s t ru c tio n m e m o r y P C b . P ro g r a m c o u n te r c. ALU register contents address d. registers a d d r e s s value value e. Data memory 5 5.1 Introduction basic architecture There are some similarities worth noting All instructions use the ALU after reading the registers data-transfer class, for address calculations arithmetic/logical class, for operation execution branch class, for comparisons Registers Register # Data Register # Data Memory Address Data Register # PC Instruction ALU Instruction Memory Address 6 5.1 Introduction Combinational v. State Elements Combinational Elements elements that do not possess memory (ALU) output depends only on input same input, same output State or sequential Elements elements that possess memory or state (registers, instruction memory, data memory) output depends on input and state input consists of data and clock clock determines when element can be written 7 which are combinational? which are state? In s tr u c tio n a d d r e s s In s tr u c tio n a . In s t ru c tio n m e m o r y P C b . P ro g r a m c o u n te r c. ALU register contents address d. registers a d d r e s s value value e. Data memory 8 5.1 Introduction Clocking Methodology Clock cycle Read state element 1 Combinational logic Write state element 2 state element 1 must be read and state element 2 written in the same cycle State element Combinational logic state element is read, processed and written in the same cycle 9 5.2 Execution Cycle 1. Fetch the instruction (and increment PC) 2. Decode the instruction 3. Fetch the data 4. Process the data 5. Store the results 1. Fetch the (next) instruction 10 5.3 Building a Datapath Single clock cycle P C In stru c tio n a d d r e s s In s tru c tio n a . In s t ru c tio n m e m o r y b . P r o g r a m c o u n te r A d d S u m c . A d d e r Elements needed to build a fetch datapath 11 5.3 Building a Datapath Fetch Instruction and Increment PC...
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CS312-CH5 - 1 Ch 5 The Processor 5.1 Introduction 5.2...

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