Unformatted text preview: fixed capacitance C L with a rising step (0 Æ V DD ) at its input. Your expression for the delay should be in terms of W, L, R sq , C L , C G (effective gate capacitance per μm of width), and C D (effective diffusion capacitance per μm of width)....
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- Spring '08
- Integrated Circuit, 3 pts, 4 pts, Vdd, VIH, effective gate capacitance, effective diffusion capacitance