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Unformatted text preview: fixed capacitance C L with a rising step (0 V DD ) at its input. Your expression for the delay should be in terms of W, L, R sq , C L , C G (effective gate capacitance per m of width), and C D (effective diffusion capacitance per m of width)....
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This note was uploaded on 08/26/2009 for the course EE 141 taught by Professor Staff during the Spring '08 term at University of California, Berkeley.
- Spring '08
- Integrated Circuit