ee141_fa07_mt1-2 - fixed capacitance C L with a rising step...

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EECS 141: FALL 2007 – MIDTERM 1 3/9 b) (3 pts) Please draw the VTC of a p dynamic inverter as its input is swept from V DD to 0V. Remember that the output of a p inverter is initially discharged to Gnd. Please also provide the values of V OH , V OL , V IH , and V IL . c) (4 pts) Now we’ll look at the sizing of a chain of such dynamic inverters. Using the RC model, write an equation for the delay of an n gate of width W driving a
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Unformatted text preview: fixed capacitance C L with a rising step (0 V DD ) at its input. Your expression for the delay should be in terms of W, L, R sq , C L , C G (effective gate capacitance per m of width), and C D (effective diffusion capacitance per m of width)....
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This note was uploaded on 08/26/2009 for the course EE 141 taught by Professor Staff during the Spring '08 term at University of California, Berkeley.

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