ee141_fa07_mt1-6 - ox C ov L L S C j,bottom C j,sidewall C...

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
EECS 141: FALL 2007 – MIDTERM 1 7/9 b) (6 pts) Using the detailed model of transistor capacitance discussed in Lecture 7, please draw all of the capacitors connected to Out when V in = V DD on the figure below. You should also write out the equations you would use to calculate the values of these capacitors – these equations should be in terms of C
Background image of page 1
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: ox , C ov , L, L S , C j,bottom , C j,sidewall , C j,gate_edge , and the widths of the transistors. (Note that you do not need to plug in any numbers for these parameters – only write out the equations.)...
View Full Document

{[ snackBarMessage ]}

Ask a homework question - tutors are online