ee141_fa07_mt1

# ee141_fa07_mt1 - So in the figure above nodes “n1” and...

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EECS 141: FALL 2007 – MIDTERM 1 2/9 PROBLEM 1. (26 pts) Dynamic Inverters: VTC and Delay. For this problem only, you should assume that R sq,p = R sq,n = R sq . In other words, an inverter with W p = W n = 1μm would have equal rising and falling delays. Note that this means that t inv = 2·ln(2)·L·R sq ·C G . Also, V DD = 2.5V. The figure above shows a chain of 4 “dynamic inverters”; every cycle, before the inverters are used, their outputs are set to a well-known state through transistors not shown here (which you can assume are negligibly small compared to the transistors in the inverter). Specifically, for an “n” dynamic inverter, its output starts at V DD (2.5V), and for a “p” dynamic inverter the output starts at Gnd (0V).
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Unformatted text preview: So, in the figure above, nodes “n1” and “n3” would be initially charged to V DD , and nodes “n2” and “Out” would be initially discharged to Gnd (0V). Once these initial voltages have been set, no transistors drive the output until there is a rising transition at the input of an n inverter, or a falling transition at the input of a p inverter. In other words, the inverter’s output voltage is simply stored on the capacitance at its output. a) (3 pts) Please draw the VTC of an n dynamic inverter as its input is swept from 0V to V DD . Remember that the output of an n inverter is initially charged to V DD . Please also provide the values of V OH , V OL , V IH , and V IL ....
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